6f166312c6
The Marvell Armada 38x SoC introduce new features to the XOR engine, especially the fact that the engine mode (MEMCPY/XOR/PQ/etc) can be part of the descriptor and not set through the controller registers. This new feature allows mixing of different commands (even PQ) on the same channel/chain without the need to stop the engine to reconfigure the engine mode. Refactor the driver to be able to use that new feature on the Armada 38x, while keeping the old behaviour on the older SoCs. Signed-off-by: Lior Amsalem <alior@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
41 lines
1.1 KiB
Plaintext
41 lines
1.1 KiB
Plaintext
* Marvell XOR engines
|
|
|
|
Required properties:
|
|
- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
|
|
- reg: Should contain registers location and length (two sets)
|
|
the first set is the low registers, the second set the high
|
|
registers for the XOR engine.
|
|
- clocks: pointer to the reference clock
|
|
|
|
The DT node must also contains sub-nodes for each XOR channel that the
|
|
XOR engine has. Those sub-nodes have the following required
|
|
properties:
|
|
- interrupts: interrupt of the XOR channel
|
|
|
|
And the following optional properties:
|
|
- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
|
|
- dmacap,memset to indicate that the XOR channel is capable of memset operations
|
|
- dmacap,xor to indicate that the XOR channel is capable of xor operations
|
|
|
|
Example:
|
|
|
|
xor@d0060900 {
|
|
compatible = "marvell,orion-xor";
|
|
reg = <0xd0060900 0x100
|
|
0xd0060b00 0x100>;
|
|
clocks = <&coreclk 0>;
|
|
status = "okay";
|
|
|
|
xor00 {
|
|
interrupts = <51>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
xor01 {
|
|
interrupts = <52>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
dmacap,memset;
|
|
};
|
|
};
|