38305907ef
Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
106 lines
2.7 KiB
C
106 lines
2.7 KiB
C
/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MDP5_CFG_H__
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#define __MDP5_CFG_H__
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#include "msm_drv.h"
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/*
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* mdp5_cfg
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*
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* This module configures the dynamic offsets used by mdp5.xml.h
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* (initialized in mdp5_cfg.c)
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*/
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extern const struct mdp5_cfg_hw *mdp5_cfg;
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#define MAX_CTL 8
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#define MAX_BASES 8
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#define MAX_SMP_BLOCKS 44
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#define MAX_CLIENTS 32
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typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);
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#define MDP5_SUB_BLOCK_DEFINITION \
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int count; \
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uint32_t base[MAX_BASES]
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struct mdp5_sub_block {
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MDP5_SUB_BLOCK_DEFINITION;
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};
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struct mdp5_lm_block {
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MDP5_SUB_BLOCK_DEFINITION;
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uint32_t nb_stages; /* number of stages per blender */
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};
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struct mdp5_ctl_block {
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MDP5_SUB_BLOCK_DEFINITION;
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uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
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};
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struct mdp5_smp_block {
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int mmb_count; /* number of SMP MMBs */
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int mmb_size; /* MMB: size in bytes */
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mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
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int reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */
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};
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#define MDP5_INTF_NUM_MAX 5
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struct mdp5_cfg_hw {
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char *name;
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struct mdp5_smp_block smp;
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struct mdp5_ctl_block ctl;
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struct mdp5_sub_block pipe_vig;
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struct mdp5_sub_block pipe_rgb;
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struct mdp5_sub_block pipe_dma;
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struct mdp5_lm_block lm;
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struct mdp5_sub_block dspp;
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struct mdp5_sub_block ad;
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struct mdp5_sub_block pp;
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struct mdp5_sub_block intf;
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u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
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uint32_t max_clk;
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};
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/* platform config data (ie. from DT, or pdata) */
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struct mdp5_cfg_platform {
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struct iommu_domain *iommu;
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};
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struct mdp5_cfg {
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const struct mdp5_cfg_hw *hw;
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struct mdp5_cfg_platform platform;
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};
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struct mdp5_kms;
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struct mdp5_cfg_handler;
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const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_hnd);
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struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
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int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);
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#define mdp5_cfg_intf_is_virtual(intf_type) ({ \
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typeof(intf_type) __val = (intf_type); \
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(__val) >= INTF_VIRTUAL ? true : false; })
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struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
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uint32_t major, uint32_t minor);
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void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
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#endif /* __MDP5_CFG_H__ */
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