Rodrigo Siqueira d1dcb05f0e drm/amd/include: Add OCSC registers ... Add registers for handling Post Gamma Color Blending (OCSC), which is useful for conversion from RGB->YUV for HDMI. Reviewed-by: Leo Li <sunpeng.li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-01-16 13:41:06 -05:00
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asic_reg	drm/amd/include: Add OCSC registers	2020-01-16 13:41:06 -05:00
ivsrcid
amd_acpi.h
amd_pcie_helpers.h
amd_pcie.h
amd_shared.h	drm/amdgpu: add JPEG PG and CG interface	2019-11-19 10:12:50 -05:00
arct_ip_offset.h
atom-bits.h
atom-names.h
atom-types.h
atombios.h
atomfirmware.h	drm/amdgpu: update the method to get fb_loc of memory training(V4)	2019-12-23 14:59:20 -05:00
atomfirmwareid.h
cgs_common.h
cik_structs.h
discovery.h	drm/amdgpu/discovery: reserve discovery data at the top of VRAM	2019-10-15 15:48:46 -04:00
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h	drm/amdkfd: use kiq to load the mqd of hiq queue for gfx v9 (v6)	2020-01-16 13:34:50 -05:00
kgd_pp_interface.h	drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2	2019-11-06 16:27:46 -05:00
navi10_enum.h
navi10_ip_offset.h
navi12_ip_offset.h
navi14_ip_offset.h
pptable.h
renoir_ip_offset.h	drm/amd/display: Add DCN_BASE regs	2019-10-17 16:27:27 -04:00
soc15_hw_ip.h
soc15_ih_clientid.h
v9_structs.h
v10_structs.h
vega10_enum.h	drm/amdgpu: Support new arcturus mtype	2019-09-13 17:35:48 -05:00
vega10_ip_offset.h
vega20_ip_offset.h
vi_structs.h