34b34ee07d
HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef RVU_H
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#define RVU_H
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#include "rvu_struct.h"
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#include "mbox.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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/* PCI BAR nos */
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#define PCI_AF_REG_BAR_NUM 0
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#define PCI_PF_REG_BAR_NUM 2
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#define PCI_MBOX_BAR_NUM 4
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#define NAME_SIZE 32
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/* PF_FUNC */
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#define RVU_PFVF_PF_SHIFT 10
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#define RVU_PFVF_PF_MASK 0x3F
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#define RVU_PFVF_FUNC_SHIFT 0
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#define RVU_PFVF_FUNC_MASK 0x3FF
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struct rvu_work {
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struct work_struct work;
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struct rvu *rvu;
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};
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struct rsrc_bmap {
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unsigned long *bmap; /* Pointer to resource bitmap */
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u16 max; /* Max resource id or count */
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};
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struct rvu_block {
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struct rsrc_bmap lf;
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u16 *fn_map; /* LF to pcifunc mapping */
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bool multislot;
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bool implemented;
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u8 addr; /* RVU_BLOCK_ADDR_E */
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u8 type; /* RVU_BLOCK_TYPE_E */
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u8 lfshift;
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u64 lookup_reg;
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u64 pf_lfcnt_reg;
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u64 vf_lfcnt_reg;
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u64 lfcfg_reg;
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u64 msixcfg_reg;
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u64 lfreset_reg;
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unsigned char name[NAME_SIZE];
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};
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/* Structure for per RVU func info ie PF/VF */
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struct rvu_pfvf {
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bool npalf; /* Only one NPALF per RVU_FUNC */
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bool nixlf; /* Only one NIXLF per RVU_FUNC */
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u16 sso;
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u16 ssow;
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u16 cptlfs;
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u16 timlfs;
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/* Block LF's MSIX vector info */
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struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
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#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
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u16 *msix_lfmap; /* Vector to block LF mapping */
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};
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struct rvu_hwinfo {
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u8 total_pfs; /* MAX RVU PFs HW supports */
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u16 total_vfs; /* Max RVU VFs HW supports */
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u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
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struct rvu_block block[BLK_COUNT]; /* Block info */
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};
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struct rvu {
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void __iomem *afreg_base;
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void __iomem *pfreg_base;
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struct pci_dev *pdev;
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struct device *dev;
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struct rvu_hwinfo *hw;
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struct rvu_pfvf *pf;
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struct rvu_pfvf *hwvf;
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spinlock_t rsrc_lock; /* Serialize resource alloc/free */
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/* Mbox */
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struct otx2_mbox mbox;
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struct rvu_work *mbox_wrk;
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struct workqueue_struct *mbox_wq;
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/* MSI-X */
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u16 num_vec;
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char *irq_name;
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bool *irq_allocated;
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dma_addr_t msix_base_iova;
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};
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static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
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{
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writeq(val, rvu->afreg_base + ((block << 28) | offset));
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}
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static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
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{
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return readq(rvu->afreg_base + ((block << 28) | offset));
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}
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static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
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{
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writeq(val, rvu->pfreg_base + offset);
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}
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static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
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{
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return readq(rvu->pfreg_base + offset);
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}
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/* Function Prototypes
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* RVU
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*/
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int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
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int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
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void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
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int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
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int rvu_get_pf(u16 pcifunc);
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struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
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void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
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bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
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int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
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int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
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int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
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#endif /* RVU_H */
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