forked from Minki/linux
737d0bb770
Patch from George G. Davis Fix leading, trailing and other miscellaneous whitespace issues in arch/arm/kernel/alignment.c. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
808 lines
20 KiB
C
808 lines
20 KiB
C
/*
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* linux/arch/arm/mm/alignment.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Modifications for ARM processor (c) 1995-2001 Russell King
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* Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
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* - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
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* Copyright (C) 1996, Cygnus Software Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <asm/unaligned.h>
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#include "fault.h"
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/*
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* 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
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* /proc/sys/debug/alignment, modified and integrated into
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* Linux 2.1 by Russell King
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*
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* Speed optimisations and better fault handling by Russell King.
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*
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* *** NOTE ***
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* This code is not portable to processors with late data abort handling.
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*/
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#define CODING_BITS(i) (i & 0x0e000000)
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#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
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#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
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#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
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#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
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#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
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#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
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#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
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#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
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#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
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#define RD_BITS(i) ((i >> 12) & 15) /* Rd */
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#define RM_BITS(i) (i & 15) /* Rm */
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#define REGMASK_BITS(i) (i & 0xffff)
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#define OFFSET_BITS(i) (i & 0x0fff)
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#define IS_SHIFT(i) (i & 0x0ff0)
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#define SHIFT_BITS(i) ((i >> 7) & 0x1f)
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#define SHIFT_TYPE(i) (i & 0x60)
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#define SHIFT_LSL 0x00
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#define SHIFT_LSR 0x20
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#define SHIFT_ASR 0x40
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#define SHIFT_RORRRX 0x60
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static unsigned long ai_user;
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static unsigned long ai_sys;
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static unsigned long ai_skipped;
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static unsigned long ai_half;
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static unsigned long ai_word;
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static unsigned long ai_dword;
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static unsigned long ai_multi;
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static int ai_usermode;
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#ifdef CONFIG_PROC_FS
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static const char *usermode_action[] = {
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"ignored",
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"warn",
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"fixup",
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"fixup+warn",
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"signal",
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"signal+warn"
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};
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static int
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proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
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void *data)
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{
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char *p = page;
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int len;
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p += sprintf(p, "User:\t\t%lu\n", ai_user);
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p += sprintf(p, "System:\t\t%lu\n", ai_sys);
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p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
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p += sprintf(p, "Half:\t\t%lu\n", ai_half);
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p += sprintf(p, "Word:\t\t%lu\n", ai_word);
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if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
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p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
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p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
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p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
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usermode_action[ai_usermode]);
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len = (p - page) - off;
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if (len < 0)
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len = 0;
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*eof = (len <= count) ? 1 : 0;
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*start = page + off;
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return len;
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}
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static int proc_alignment_write(struct file *file, const char __user *buffer,
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unsigned long count, void *data)
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{
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char mode;
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if (count > 0) {
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if (get_user(mode, buffer))
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return -EFAULT;
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if (mode >= '0' && mode <= '5')
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ai_usermode = mode - '0';
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}
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return count;
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}
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#endif /* CONFIG_PROC_FS */
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union offset_union {
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unsigned long un;
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signed long sn;
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};
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#define TYPE_ERROR 0
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#define TYPE_FAULT 1
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#define TYPE_LDST 2
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#define TYPE_DONE 3
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#ifdef __ARMEB__
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#define BE 1
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#define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
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#define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
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#define NEXT_BYTE "ror #24"
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#else
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#define BE 0
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#define FIRST_BYTE_16
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#define FIRST_BYTE_32
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#define NEXT_BYTE "lsr #8"
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#endif
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#define __get8_unaligned_check(ins,val,addr,err) \
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__asm__( \
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"1: "ins" %1, [%2], #1\n" \
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"2:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 2\n" \
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"3: mov %0, #1\n" \
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" b 2b\n" \
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" .previous\n" \
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" .section __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 3b\n" \
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" .previous\n" \
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: "=r" (err), "=&r" (val), "=r" (addr) \
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: "0" (err), "2" (addr))
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#define __get16_unaligned_check(ins,val,addr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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__get8_unaligned_check(ins,v,a,err); \
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val = v << ((BE) ? 8 : 0); \
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__get8_unaligned_check(ins,v,a,err); \
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val |= v << ((BE) ? 0 : 8); \
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if (err) \
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goto fault; \
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} while (0)
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#define get16_unaligned_check(val,addr) \
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__get16_unaligned_check("ldrb",val,addr)
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#define get16t_unaligned_check(val,addr) \
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__get16_unaligned_check("ldrbt",val,addr)
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#define __get32_unaligned_check(ins,val,addr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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__get8_unaligned_check(ins,v,a,err); \
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val = v << ((BE) ? 24 : 0); \
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__get8_unaligned_check(ins,v,a,err); \
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val |= v << ((BE) ? 16 : 8); \
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__get8_unaligned_check(ins,v,a,err); \
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val |= v << ((BE) ? 8 : 16); \
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__get8_unaligned_check(ins,v,a,err); \
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val |= v << ((BE) ? 0 : 24); \
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if (err) \
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goto fault; \
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} while (0)
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#define get32_unaligned_check(val,addr) \
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__get32_unaligned_check("ldrb",val,addr)
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#define get32t_unaligned_check(val,addr) \
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__get32_unaligned_check("ldrbt",val,addr)
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#define __put16_unaligned_check(ins,val,addr) \
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( FIRST_BYTE_16 \
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"1: "ins" %1, [%2], #1\n" \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"2: "ins" %1, [%2]\n" \
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"3:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %0, #1\n" \
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" b 3b\n" \
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" .previous\n" \
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" .section __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 4b\n" \
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" .long 2b, 4b\n" \
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" .previous\n" \
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: "=r" (err), "=&r" (v), "=&r" (a) \
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: "0" (err), "1" (v), "2" (a)); \
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if (err) \
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goto fault; \
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} while (0)
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#define put16_unaligned_check(val,addr) \
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__put16_unaligned_check("strb",val,addr)
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#define put16t_unaligned_check(val,addr) \
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__put16_unaligned_check("strbt",val,addr)
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#define __put32_unaligned_check(ins,val,addr) \
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( FIRST_BYTE_32 \
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"1: "ins" %1, [%2], #1\n" \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"2: "ins" %1, [%2], #1\n" \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"3: "ins" %1, [%2], #1\n" \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"4: "ins" %1, [%2]\n" \
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"5:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 2\n" \
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"6: mov %0, #1\n" \
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" b 5b\n" \
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" .previous\n" \
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" .section __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 6b\n" \
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" .long 2b, 6b\n" \
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" .long 3b, 6b\n" \
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" .long 4b, 6b\n" \
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" .previous\n" \
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: "=r" (err), "=&r" (v), "=&r" (a) \
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: "0" (err), "1" (v), "2" (a)); \
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if (err) \
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goto fault; \
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} while (0)
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#define put32_unaligned_check(val,addr) \
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__put32_unaligned_check("strb", val, addr)
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#define put32t_unaligned_check(val,addr) \
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__put32_unaligned_check("strbt", val, addr)
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static void
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do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
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{
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if (!LDST_U_BIT(instr))
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offset.un = -offset.un;
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if (!LDST_P_BIT(instr))
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addr += offset.un;
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if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
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regs->uregs[RN_BITS(instr)] = addr;
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}
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static int
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do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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ai_half += 1;
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if (user_mode(regs))
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goto user;
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if (LDST_L_BIT(instr)) {
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unsigned long val;
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get16_unaligned_check(val, addr);
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/* signed half-word? */
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if (instr & 0x40)
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val = (signed long)((signed short) val);
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regs->uregs[rd] = val;
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} else
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put16_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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user:
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if (LDST_L_BIT(instr)) {
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unsigned long val;
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get16t_unaligned_check(val, addr);
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/* signed half-word? */
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if (instr & 0x40)
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val = (signed long)((signed short) val);
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regs->uregs[rd] = val;
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} else
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put16t_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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fault:
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return TYPE_FAULT;
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}
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static int
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do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
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struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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if (((rd & 1) == 1) || (rd == 14))
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goto bad;
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ai_dword += 1;
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if (user_mode(regs))
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goto user;
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if ((instr & 0xf0) == 0xd0) {
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unsigned long val;
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get32_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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get32_unaligned_check(val, addr + 4);
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regs->uregs[rd + 1] = val;
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} else {
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put32_unaligned_check(regs->uregs[rd], addr);
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put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
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}
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return TYPE_LDST;
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user:
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if ((instr & 0xf0) == 0xd0) {
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unsigned long val;
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get32t_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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get32t_unaligned_check(val, addr + 4);
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regs->uregs[rd + 1] = val;
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} else {
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put32t_unaligned_check(regs->uregs[rd], addr);
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put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
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}
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return TYPE_LDST;
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bad:
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return TYPE_ERROR;
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fault:
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return TYPE_FAULT;
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}
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static int
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do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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ai_word += 1;
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if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
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goto trans;
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if (LDST_L_BIT(instr)) {
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unsigned int val;
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get32_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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} else
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put32_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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trans:
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if (LDST_L_BIT(instr)) {
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unsigned int val;
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get32t_unaligned_check(val, addr);
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regs->uregs[rd] = val;
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} else
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put32t_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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fault:
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return TYPE_FAULT;
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}
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/*
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* LDM/STM alignment handler.
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*
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* There are 4 variants of this instruction:
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*
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* B = rn pointer before instruction, A = rn pointer after instruction
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* ------ increasing address ----->
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* | | r0 | r1 | ... | rx | |
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* PU = 01 B A
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* PU = 11 B A
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* PU = 00 A B
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* PU = 10 A B
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*/
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static int
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do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
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{
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unsigned int rd, rn, correction, nr_regs, regbits;
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unsigned long eaddr, newaddr;
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if (LDM_S_BIT(instr))
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goto bad;
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correction = 4; /* processor implementation defined */
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regs->ARM_pc += correction;
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ai_multi += 1;
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/* count the number of registers in the mask to be transferred */
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nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
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rn = RN_BITS(instr);
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newaddr = eaddr = regs->uregs[rn];
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if (!LDST_U_BIT(instr))
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nr_regs = -nr_regs;
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newaddr += nr_regs;
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if (!LDST_U_BIT(instr))
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eaddr = newaddr;
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if (LDST_P_EQ_U(instr)) /* U = P */
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eaddr += 4;
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/*
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* For alignment faults on the ARM922T/ARM920T the MMU makes
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* the FSR (and hence addr) equal to the updated base address
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* of the multiple access rather than the restored value.
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* Switch this message off if we've got a ARM92[02], otherwise
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* [ls]dm alignment faults are noisy!
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*/
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#if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
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/*
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* This is a "hint" - we already have eaddr worked out by the
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* processor for us.
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*/
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if (addr != eaddr) {
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printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
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"addr = %08lx, eaddr = %08lx\n",
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instruction_pointer(regs), instr, addr, eaddr);
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show_regs(regs);
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}
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#endif
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if (user_mode(regs)) {
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for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
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regbits >>= 1, rd += 1)
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if (regbits & 1) {
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if (LDST_L_BIT(instr)) {
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unsigned int val;
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get32t_unaligned_check(val, eaddr);
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regs->uregs[rd] = val;
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} else
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put32t_unaligned_check(regs->uregs[rd], eaddr);
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eaddr += 4;
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}
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} else {
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for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
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regbits >>= 1, rd += 1)
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if (regbits & 1) {
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if (LDST_L_BIT(instr)) {
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unsigned int val;
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get32_unaligned_check(val, eaddr);
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regs->uregs[rd] = val;
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} else
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put32_unaligned_check(regs->uregs[rd], eaddr);
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eaddr += 4;
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}
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}
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if (LDST_W_BIT(instr))
|
|
regs->uregs[rn] = newaddr;
|
|
if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
|
|
regs->ARM_pc -= correction;
|
|
return TYPE_DONE;
|
|
|
|
fault:
|
|
regs->ARM_pc -= correction;
|
|
return TYPE_FAULT;
|
|
|
|
bad:
|
|
printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
|
|
return TYPE_ERROR;
|
|
}
|
|
|
|
/*
|
|
* Convert Thumb ld/st instruction forms to equivalent ARM instructions so
|
|
* we can reuse ARM userland alignment fault fixups for Thumb.
|
|
*
|
|
* This implementation was initially based on the algorithm found in
|
|
* gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
|
|
* to convert only Thumb ld/st instruction forms to equivalent ARM forms.
|
|
*
|
|
* NOTES:
|
|
* 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
|
|
* 2. If for some reason we're passed an non-ld/st Thumb instruction to
|
|
* decode, we return 0xdeadc0de. This should never happen under normal
|
|
* circumstances but if it does, we've got other problems to deal with
|
|
* elsewhere and we obviously can't fix those problems here.
|
|
*/
|
|
|
|
static unsigned long
|
|
thumb2arm(u16 tinstr)
|
|
{
|
|
u32 L = (tinstr & (1<<11)) >> 11;
|
|
|
|
switch ((tinstr & 0xf800) >> 11) {
|
|
/* 6.5.1 Format 1: */
|
|
case 0x6000 >> 11: /* 7.1.52 STR(1) */
|
|
case 0x6800 >> 11: /* 7.1.26 LDR(1) */
|
|
case 0x7000 >> 11: /* 7.1.55 STRB(1) */
|
|
case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
|
|
return 0xe5800000 |
|
|
((tinstr & (1<<12)) << (22-12)) | /* fixup */
|
|
(L<<20) | /* L==1? */
|
|
((tinstr & (7<<0)) << (12-0)) | /* Rd */
|
|
((tinstr & (7<<3)) << (16-3)) | /* Rn */
|
|
((tinstr & (31<<6)) >> /* immed_5 */
|
|
(6 - ((tinstr & (1<<12)) ? 0 : 2)));
|
|
case 0x8000 >> 11: /* 7.1.57 STRH(1) */
|
|
case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
|
|
return 0xe1c000b0 |
|
|
(L<<20) | /* L==1? */
|
|
((tinstr & (7<<0)) << (12-0)) | /* Rd */
|
|
((tinstr & (7<<3)) << (16-3)) | /* Rn */
|
|
((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
|
|
((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
|
|
|
|
/* 6.5.1 Format 2: */
|
|
case 0x5000 >> 11:
|
|
case 0x5800 >> 11:
|
|
{
|
|
static const u32 subset[8] = {
|
|
0xe7800000, /* 7.1.53 STR(2) */
|
|
0xe18000b0, /* 7.1.58 STRH(2) */
|
|
0xe7c00000, /* 7.1.56 STRB(2) */
|
|
0xe19000d0, /* 7.1.34 LDRSB */
|
|
0xe7900000, /* 7.1.27 LDR(2) */
|
|
0xe19000b0, /* 7.1.33 LDRH(2) */
|
|
0xe7d00000, /* 7.1.31 LDRB(2) */
|
|
0xe19000f0 /* 7.1.35 LDRSH */
|
|
};
|
|
return subset[(tinstr & (7<<9)) >> 9] |
|
|
((tinstr & (7<<0)) << (12-0)) | /* Rd */
|
|
((tinstr & (7<<3)) << (16-3)) | /* Rn */
|
|
((tinstr & (7<<6)) >> (6-0)); /* Rm */
|
|
}
|
|
|
|
/* 6.5.1 Format 3: */
|
|
case 0x4800 >> 11: /* 7.1.28 LDR(3) */
|
|
/* NOTE: This case is not technically possible. We're
|
|
* loading 32-bit memory data via PC relative
|
|
* addressing mode. So we can and should eliminate
|
|
* this case. But I'll leave it here for now.
|
|
*/
|
|
return 0xe59f0000 |
|
|
((tinstr & (7<<8)) << (12-8)) | /* Rd */
|
|
((tinstr & 255) << (2-0)); /* immed_8 */
|
|
|
|
/* 6.5.1 Format 4: */
|
|
case 0x9000 >> 11: /* 7.1.54 STR(3) */
|
|
case 0x9800 >> 11: /* 7.1.29 LDR(4) */
|
|
return 0xe58d0000 |
|
|
(L<<20) | /* L==1? */
|
|
((tinstr & (7<<8)) << (12-8)) | /* Rd */
|
|
((tinstr & 255) << 2); /* immed_8 */
|
|
|
|
/* 6.6.1 Format 1: */
|
|
case 0xc000 >> 11: /* 7.1.51 STMIA */
|
|
case 0xc800 >> 11: /* 7.1.25 LDMIA */
|
|
{
|
|
u32 Rn = (tinstr & (7<<8)) >> 8;
|
|
u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
|
|
|
|
return 0xe8800000 | W | (L<<20) | (Rn<<16) |
|
|
(tinstr&255);
|
|
}
|
|
|
|
/* 6.6.1 Format 2: */
|
|
case 0xb000 >> 11: /* 7.1.48 PUSH */
|
|
case 0xb800 >> 11: /* 7.1.47 POP */
|
|
if ((tinstr & (3 << 9)) == 0x0400) {
|
|
static const u32 subset[4] = {
|
|
0xe92d0000, /* STMDB sp!,{registers} */
|
|
0xe92d4000, /* STMDB sp!,{registers,lr} */
|
|
0xe8bd0000, /* LDMIA sp!,{registers} */
|
|
0xe8bd8000 /* LDMIA sp!,{registers,pc} */
|
|
};
|
|
return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
|
|
(tinstr & 255); /* register_list */
|
|
}
|
|
/* Else fall through for illegal instruction case */
|
|
|
|
default:
|
|
return 0xdeadc0de;
|
|
}
|
|
}
|
|
|
|
static int
|
|
do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
|
{
|
|
union offset_union offset;
|
|
unsigned long instr = 0, instrptr;
|
|
int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
|
|
unsigned int type;
|
|
mm_segment_t fs;
|
|
unsigned int fault;
|
|
u16 tinstr = 0;
|
|
|
|
instrptr = instruction_pointer(regs);
|
|
|
|
fs = get_fs();
|
|
set_fs(KERNEL_DS);
|
|
if thumb_mode(regs) {
|
|
fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
|
|
if (!(fault))
|
|
instr = thumb2arm(tinstr);
|
|
} else
|
|
fault = __get_user(instr, (u32 *)instrptr);
|
|
set_fs(fs);
|
|
|
|
if (fault) {
|
|
type = TYPE_FAULT;
|
|
goto bad_or_fault;
|
|
}
|
|
|
|
if (user_mode(regs))
|
|
goto user;
|
|
|
|
ai_sys += 1;
|
|
|
|
fixup:
|
|
|
|
regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
|
|
|
|
switch (CODING_BITS(instr)) {
|
|
case 0x00000000: /* 3.13.4 load/store instruction extensions */
|
|
if (LDSTHD_I_BIT(instr))
|
|
offset.un = (instr & 0xf00) >> 4 | (instr & 15);
|
|
else
|
|
offset.un = regs->uregs[RM_BITS(instr)];
|
|
|
|
if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
|
|
(instr & 0x001000f0) == 0x001000f0) /* LDRSH */
|
|
handler = do_alignment_ldrhstrh;
|
|
else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
|
|
(instr & 0x001000f0) == 0x000000f0) /* STRD */
|
|
handler = do_alignment_ldrdstrd;
|
|
else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
|
|
goto swp;
|
|
else
|
|
goto bad;
|
|
break;
|
|
|
|
case 0x04000000: /* ldr or str immediate */
|
|
offset.un = OFFSET_BITS(instr);
|
|
handler = do_alignment_ldrstr;
|
|
break;
|
|
|
|
case 0x06000000: /* ldr or str register */
|
|
offset.un = regs->uregs[RM_BITS(instr)];
|
|
|
|
if (IS_SHIFT(instr)) {
|
|
unsigned int shiftval = SHIFT_BITS(instr);
|
|
|
|
switch(SHIFT_TYPE(instr)) {
|
|
case SHIFT_LSL:
|
|
offset.un <<= shiftval;
|
|
break;
|
|
|
|
case SHIFT_LSR:
|
|
offset.un >>= shiftval;
|
|
break;
|
|
|
|
case SHIFT_ASR:
|
|
offset.sn >>= shiftval;
|
|
break;
|
|
|
|
case SHIFT_RORRRX:
|
|
if (shiftval == 0) {
|
|
offset.un >>= 1;
|
|
if (regs->ARM_cpsr & PSR_C_BIT)
|
|
offset.un |= 1 << 31;
|
|
} else
|
|
offset.un = offset.un >> shiftval |
|
|
offset.un << (32 - shiftval);
|
|
break;
|
|
}
|
|
}
|
|
handler = do_alignment_ldrstr;
|
|
break;
|
|
|
|
case 0x08000000: /* ldm or stm */
|
|
handler = do_alignment_ldmstm;
|
|
break;
|
|
|
|
default:
|
|
goto bad;
|
|
}
|
|
|
|
type = handler(addr, instr, regs);
|
|
|
|
if (type == TYPE_ERROR || type == TYPE_FAULT)
|
|
goto bad_or_fault;
|
|
|
|
if (type == TYPE_LDST)
|
|
do_alignment_finish_ldst(addr, instr, regs, offset);
|
|
|
|
return 0;
|
|
|
|
bad_or_fault:
|
|
if (type == TYPE_ERROR)
|
|
goto bad;
|
|
regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
|
|
/*
|
|
* We got a fault - fix it up, or die.
|
|
*/
|
|
do_bad_area(current, current->mm, addr, fsr, regs);
|
|
return 0;
|
|
|
|
swp:
|
|
printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
|
|
|
|
bad:
|
|
/*
|
|
* Oops, we didn't handle the instruction.
|
|
*/
|
|
printk(KERN_ERR "Alignment trap: not handling instruction "
|
|
"%0*lx at [<%08lx>]\n",
|
|
thumb_mode(regs) ? 4 : 8,
|
|
thumb_mode(regs) ? tinstr : instr, instrptr);
|
|
ai_skipped += 1;
|
|
return 1;
|
|
|
|
user:
|
|
ai_user += 1;
|
|
|
|
if (ai_usermode & 1)
|
|
printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
|
|
"Address=0x%08lx FSR 0x%03x\n", current->comm,
|
|
current->pid, instrptr,
|
|
thumb_mode(regs) ? 4 : 8,
|
|
thumb_mode(regs) ? tinstr : instr,
|
|
addr, fsr);
|
|
|
|
if (ai_usermode & 2)
|
|
goto fixup;
|
|
|
|
if (ai_usermode & 4)
|
|
force_sig(SIGBUS, current);
|
|
else
|
|
set_cr(cr_no_alignment);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This needs to be done after sysctl_init, otherwise sys/ will be
|
|
* overwritten. Actually, this shouldn't be in sys/ at all since
|
|
* it isn't a sysctl, and it doesn't contain sysctl information.
|
|
* We now locate it in /proc/cpu/alignment instead.
|
|
*/
|
|
static int __init alignment_init(void)
|
|
{
|
|
#ifdef CONFIG_PROC_FS
|
|
struct proc_dir_entry *res;
|
|
|
|
res = proc_mkdir("cpu", NULL);
|
|
if (!res)
|
|
return -ENOMEM;
|
|
|
|
res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
|
|
if (!res)
|
|
return -ENOMEM;
|
|
|
|
res->read_proc = proc_alignment_read;
|
|
res->write_proc = proc_alignment_write;
|
|
#endif
|
|
|
|
hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
|
|
hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
|
|
|
|
return 0;
|
|
}
|
|
|
|
fs_initcall(alignment_init);
|