2fb318ff75
timer resolution of ~32us is pretty low. v2 has 32bits resolution, so we have quite some headroom, and can use the 24MHz clock. v1 has only 16bits, so we only increase v2. So we just exchange the timrot clock in imx28. On imx23 we have timrotv1 and everything stays the same. Signed-off-by: Torben Hohn <torbenh@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
306 lines
8.5 KiB
C
306 lines
8.5 KiB
C
/*
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* Copyright (C) 2000-2001 Deep Blue Solutions
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/mach/time.h>
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#include <asm/sched_clock.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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/*
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* There are 2 versions of the timrot on Freescale MXS-based SoCs.
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* The v1 on MX23 only gets 16 bits counter, while v2 on MX28
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* extends the counter to 32 bits.
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*
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* The implementation uses two timers, one for clock_event and
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* another for clocksource. MX28 uses timrot 0 and 1, while MX23
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* uses 0 and 2.
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*/
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#define MX23_TIMROT_VERSION_OFFSET 0x0a0
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#define MX28_TIMROT_VERSION_OFFSET 0x120
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#define BP_TIMROT_MAJOR_VERSION 24
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#define BV_TIMROT_VERSION_1 0x01
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#define BV_TIMROT_VERSION_2 0x02
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#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
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/*
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* There are 4 registers for each timrotv2 instance, and 2 registers
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* for each timrotv1. So address step 0x40 in macros below strides
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* one instance of timrotv2 while two instances of timrotv1.
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*
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* As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
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* on MX28 while timrot2 on MX23.
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*/
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/* common between v1 and v2 */
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#define HW_TIMROT_ROTCTRL 0x00
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#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
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/* v1 only */
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#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
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/* v2 only */
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#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
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#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
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#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
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#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
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#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
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#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
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#define BP_TIMROT_TIMCTRLn_SELECT 0
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#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
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#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
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#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
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static struct clock_event_device mxs_clockevent_device;
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static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
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static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
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static u32 timrot_major_version;
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static inline void timrot_irq_disable(void)
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{
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__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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}
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static inline void timrot_irq_enable(void)
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{
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__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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}
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static void timrot_irq_acknowledge(void)
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{
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__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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}
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static cycle_t timrotv1_get_cycles(struct clocksource *cs)
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{
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return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
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& 0xffff0000) >> 16);
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}
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static int timrotv1_set_next_event(unsigned long evt,
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struct clock_event_device *dev)
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{
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/* timrot decrements the count */
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__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
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return 0;
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}
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static int timrotv2_set_next_event(unsigned long evt,
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struct clock_event_device *dev)
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{
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/* timrot decrements the count */
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__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
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return 0;
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}
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static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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timrot_irq_acknowledge();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction mxs_timer_irq = {
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.name = "MXS Timer Tick",
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.dev_id = &mxs_clockevent_device,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = mxs_timer_interrupt,
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};
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#ifdef DEBUG
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static const char *clock_event_mode_label[] const = {
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[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
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[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
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[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
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[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
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};
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#endif /* DEBUG */
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static void mxs_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Disable interrupt in timer module */
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timrot_irq_disable();
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if (mode != mxs_clockevent_mode) {
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/* Set event time into the furthest future */
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if (timrot_is_v1())
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__raw_writel(0xffff,
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mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
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else
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__raw_writel(0xffffffff,
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mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
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/* Clear pending interrupt */
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timrot_irq_acknowledge();
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}
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#ifdef DEBUG
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pr_info("%s: changing mode from %s to %s\n", __func__,
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clock_event_mode_label[mxs_clockevent_mode],
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clock_event_mode_label[mode]);
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#endif /* DEBUG */
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/* Remember timer mode */
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mxs_clockevent_mode = mode;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_err("%s: Periodic mode is not implemented\n", __func__);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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timrot_irq_enable();
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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/* Left event sources disabled, no more interrupts appear */
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break;
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}
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}
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static struct clock_event_device mxs_clockevent_device = {
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.name = "mxs_timrot",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = mxs_set_mode,
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.set_next_event = timrotv2_set_next_event,
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.rating = 200,
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};
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static int __init mxs_clockevent_init(struct clk *timer_clk)
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{
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if (timrot_is_v1())
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mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
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mxs_clockevent_device.cpumask = cpumask_of(0);
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clockevents_config_and_register(&mxs_clockevent_device,
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clk_get_rate(timer_clk), 0xf,
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timrot_is_v1() ? 0xfffe : 0xfffffffe);
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return 0;
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}
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static struct clocksource clocksource_mxs = {
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.name = "mxs_timer",
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.rating = 200,
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.read = timrotv1_get_cycles,
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.mask = CLOCKSOURCE_MASK(16),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static u32 notrace mxs_read_sched_clock_v2(void)
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{
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return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
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}
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static int __init mxs_clocksource_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (timrot_is_v1())
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clocksource_register_hz(&clocksource_mxs, c);
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else {
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clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
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"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
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setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
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}
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return 0;
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}
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void __init mxs_timer_init(void)
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{
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struct device_node *np;
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struct clk *timer_clk;
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int irq;
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np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
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if (!np) {
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pr_err("%s: failed find timrot node\n", __func__);
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return;
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}
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timer_clk = clk_get_sys("timrot", NULL);
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if (IS_ERR(timer_clk)) {
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pr_err("%s: failed to get clk\n", __func__);
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return;
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}
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clk_prepare_enable(timer_clk);
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/*
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* Initialize timers to a known state
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*/
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mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
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/* get timrot version */
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timrot_major_version = __raw_readl(mxs_timrot_base +
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(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
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MX28_TIMROT_VERSION_OFFSET));
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timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
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/* one for clock_event */
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__raw_writel((timrot_is_v1() ?
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BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
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BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
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BM_TIMROT_TIMCTRLn_UPDATE |
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BM_TIMROT_TIMCTRLn_IRQ_EN,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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/* another for clocksource */
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__raw_writel((timrot_is_v1() ?
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BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
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BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
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BM_TIMROT_TIMCTRLn_RELOAD,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
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/* set clocksource timer fixed count to the maximum */
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if (timrot_is_v1())
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__raw_writel(0xffff,
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mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
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else
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__raw_writel(0xffffffff,
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mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
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/* init and register the timer to the framework */
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mxs_clocksource_init(timer_clk);
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mxs_clockevent_init(timer_clk);
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/* Make irqs happen */
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irq = irq_of_parse_and_map(np, 0);
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setup_irq(irq, &mxs_timer_irq);
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}
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