b14ffae378
Pull drm updates from Dave Airlie: "Lots of work all over, Intel improving DG2 support, amdkfd CRIU support, msm new hw support, and faster fbdev support. dma-buf: - rename dma-buf-map to iosys-map core: - move buddy allocator to core - add pci/platform init macros - improve EDID parser deep color handling - EDID timing type 7 support - add GPD Win Max quirk - add yes/no helpers to string_helpers - flatten syncobj chains - add nomodeset support to lots of drivers - improve fb-helper clipping support - add default property value interface fbdev: - improve fbdev ops speed ttm: - add a backpointer from ttm bo->ttm resource dp: - move displayport headers - add a dp helper module bridge: - anx7625 atomic support, HDCP support panel: - split out panel-lvds and lvds bindings - find panels in OF subnodes privacy: - add chromeos privacy screen support fb: - hot unplug fw fb on forced removal simpledrm: - request region instead of marking ioresource busy - add panel oreintation property udmabuf: - fix oops with 0 pages amdgpu: - power management code cleanup - Enable freesync video mode by default - RAS code cleanup - Improve VRAM access for debug using SDMA - SR-IOV rework special register access and fixes - profiling power state request ioctl - expose IP discovery via sysfs - Cyan skillfish updates - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates - expose benchmark tests via debugfs - add module param to disable XGMI for testing - GPU reset debugfs register dumping support amdkfd: - CRIU support - SDMA queue fixes radeon: - UVD suspend fix - iMac backlight fix i915: - minimal parallel submission for execlists - DG2-G12 subplatform added - DG2 programming workarounds - DG2 accelerated migration support - flat CCS and CCS engine support for XeHP - initial small BAR support - drop fake LMEM support - ADL-N PCH support - bigjoiner updates - introduce VMA resources and async unbinding - register definitions cleanups - multi-FBC refactoring - DG1 OPROM over SPI support - ADL-N platform enabling - opregion mailbox #5 support - DP MST ESI improvements - drm device based logging - async flip optimisation for DG2 - CPU arch abstraction fixes - improve GuC ADS init to work on aarch64 - tweak TTM LRU priority hint - GuC 69.0.3 support - remove short term execbuf pins nouveau: - higher DP/eDP bitrates - backlight fixes msm: - dpu + dp support for sc8180x - dp support for sm8350 - dpu + dsi support for qcm2290 - 10nm dsi phy tuning support - bridge support for dp encoder - gpu support for additional 7c3 SKUs ingenic: - HDMI support for JZ4780 - aux channel EDID support ast: - AST2600 support - add wide screen support - create DP/DVI connectors omapdrm: - fix implicit dma_buf fencing vc4: - add CSC + full range support - better display firmware handoff panfrost: - add initial dual-core GPU support stm: - new revision support - fb handover support mediatek: - transfer display binding document to yaml format. - add mt8195 display device binding. - allow commands to be sent during video mode. - add wait_for_event for crtc disable by cmdq. tegra: - YUV format support rcar-du: - LVDS support for M3-W+ (R8A77961) exynos: - BGR pixel format for FIMD device" * tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm: (1529 commits) drm/i915/display: Do not re-enable PSR after it was marked as not reliable drm/i915/display: Fix HPD short pulse handling for eDP drm/amdgpu: Use drm_mode_copy() drm/radeon: Use drm_mode_copy() drm/amdgpu: Use ternary operator in `vcn_v1_0_start()` drm/amdgpu: Remove pointless on stack mode copies drm/amd/pm: fix indenting in __smu_cmn_reg_print_error() drm/amdgpu/dc: fix typos in comments drm/amdgpu: fix typos in comments drm/amd/pm: fix typos in comments drm/amdgpu: Add stolen reserved memory for MI25 SRIOV. drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations. drm/amdkfd: evict svm bo worker handle error drm/amdgpu/vcn: fix vcn ring test failure in igt reload test drm/amdgpu: only allow secure submission on rings which support that drm/amdgpu: fixed the warnings reported by kernel test robot drm/amd/display: 3.2.177 drm/amd/display: [FW Promotion] Release 0.0.108.0 drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2 drm/amd/display: Wait for hubp read line for Pollock ...
92 lines
3.7 KiB
C
92 lines
3.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2019 Intel Corporation.
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*/
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#ifndef __INTEL_PCH__
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#define __INTEL_PCH__
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struct drm_i915_private;
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/*
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* Sorted by south display engine compatibility.
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* If the new PCH comes with a south display engine that is not
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* inherited from the latest item, please do not add it to the
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* end. Instead, add it right after its "parent" PCH.
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*/
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enum intel_pch {
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PCH_NOP = -1, /* PCH without south display */
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PCH_NONE = 0, /* No PCH present */
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PCH_IBX, /* Ibexpeak PCH */
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PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
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PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
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PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
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PCH_CNP, /* Cannon/Comet Lake PCH */
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PCH_ICP, /* Ice Lake PCH */
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PCH_JSP, /* Jasper Lake PCH */
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PCH_MCC, /* Mule Creek Canyon PCH */
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PCH_TGP, /* Tiger Lake PCH */
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PCH_ADP, /* Alder Lake PCH */
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/* Fake PCHs, functionality handled on the same PCI dev */
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PCH_DG1 = 1024,
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PCH_DG2,
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff80
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
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#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
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#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
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#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
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#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
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#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
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#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
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#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
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#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
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#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
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#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
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#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380
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#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
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#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880
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#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
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#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
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#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
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#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
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#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
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#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
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#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00
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#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480
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#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
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#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
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#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
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#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
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#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
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#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
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#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
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#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
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#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
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#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
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#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
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#define HAS_PCH_LPT_LP(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
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#define HAS_PCH_LPT_H(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
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#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
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#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
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#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
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#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
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void intel_detect_pch(struct drm_i915_private *dev_priv);
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#endif /* __INTEL_PCH__ */
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