forked from Minki/linux
2be25cac84
There are many magic numbers used in the PCIe code. Replace them with some constants from the Broadcom SDK and also use them in the pcie host controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
255 lines
6.7 KiB
C
255 lines
6.7 KiB
C
/*
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* Broadcom specific AMBA
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* PCI Core
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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/**************************************************
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* R/W ops.
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**************************************************/
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static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
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}
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#if 0
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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#endif
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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{
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u32 v;
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int i;
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
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BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= (phy << 4);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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msleep(1);
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}
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}
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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{
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_READ;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
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udelay(10);
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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}
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msleep(1);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
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u8 address, u16 data)
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{
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int max_retries = 10;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= data;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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msleep(1);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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/**************************************************
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* Workarounds.
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**************************************************/
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static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
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{
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u32 tmp;
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tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
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if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
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BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
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else
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
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}
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static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
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{
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u16 tmp;
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
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BCMA_CORE_PCI_SERDES_RX_CTRL,
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bcma_pcicore_polarity_workaround(pc));
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tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL);
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if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL,
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tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
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}
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/**************************************************
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* Init.
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**************************************************/
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static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
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{
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bcma_pcicore_serdes_workaround(pc);
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}
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static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
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{
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struct bcma_bus *bus = pc->core->bus;
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u16 chipid_top;
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chipid_top = (bus->chipinfo.id & 0xFF00);
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if (chipid_top != 0x4700 &&
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chipid_top != 0x5300)
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return false;
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#ifdef CONFIG_SSB_DRIVER_PCICORE
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if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
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return false;
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#endif /* CONFIG_SSB_DRIVER_PCICORE */
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#if 0
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/* TODO: on BCMA we use address from EROM instead of magic formula */
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u32 tmp;
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return !mips_busprobe32(tmp, (bus->mmio +
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(pc->core->core_index * BCMA_CORE_SIZE)));
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#endif
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return true;
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}
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void bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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if (pc->setup_done)
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return;
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if (bcma_core_pci_is_in_hostmode(pc)) {
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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bcma_core_pci_hostmode_init(pc);
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#else
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pr_err("Driver compiled without support for hostmode PCI\n");
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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} else {
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bcma_core_pci_clientmode_init(pc);
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}
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pc->setup_done = true;
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}
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int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
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bool enable)
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{
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struct pci_dev *pdev = pc->core->bus->host_pci;
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u32 coremask, tmp;
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int err = 0;
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if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
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/* This bcma device is not on a PCI host-bus. So the IRQs are
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* not routed through the PCI core.
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* So we must not enable routing through the PCI core. */
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goto out;
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}
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err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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coremask = BIT(core->core_index) << 8;
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if (enable)
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tmp |= coremask;
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else
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tmp &= ~coremask;
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err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
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