Ben Tebulin reported: "Since v3.7.2 on two independent machines a very specific Git repository fails in 9/10 cases on git-fsck due to an SHA1/memory failures. This only occurs on a very specific repository and can be reproduced stably on two independent laptops. Git mailing list ran out of ideas and for me this looks like some very exotic kernel issue" and bisected the failure to the backport of commit53a59fc67f
("mm: limit mmu_gather batching to fix soft lockups on !CONFIG_PREEMPT"). That commit itself is not actually buggy, but what it does is to make it much more likely to hit the partial TLB invalidation case, since it introduces a new case in tlb_next_batch() that previously only ever happened when running out of memory. The real bug is that the TLB gather virtual memory range setup is subtly buggered. It was introduced in commit597e1c3580
("mm/mmu_gather: enable tlb flush range in generic mmu_gather"), and the range handling was already fixed at least once in commite6c495a96c
("mm: fix the TLB range flushed when __tlb_remove_page() runs out of slots"), but that fix was not complete. The problem with the TLB gather virtual address range is that it isn't set up by the initial tlb_gather_mmu() initialization (which didn't get the TLB range information), but it is set up ad-hoc later by the functions that actually flush the TLB. And so any such case that forgot to update the TLB range entries would potentially miss TLB invalidates. Rather than try to figure out exactly which particular ad-hoc range setup was missing (I personally suspect it's the hugetlb case in zap_huge_pmd(), which didn't have the same logic as zap_pte_range() did), this patch just gets rid of the problem at the source: make the TLB range information available to tlb_gather_mmu(), and initialize it when initializing all the other tlb gather fields. This makes the patch larger, but conceptually much simpler. And the end result is much more understandable; even if you want to play games with partial ranges when invalidating the TLB contents in chunks, now the range information is always there, and anybody who doesn't want to bother with it won't introduce subtle bugs. Ben verified that this fixes his problem. Reported-bisected-and-tested-by: Ben Tebulin <tebulin@googlemail.com> Build-testing-by: Stephen Rothwell <sfr@canb.auug.org.au> Build-testing-by: Richard Weinberger <richard.weinberger@gmail.com> Reviewed-by: Michal Hocko <mhocko@suse.cz> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: stable@vger.kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
148 lines
4.2 KiB
C
148 lines
4.2 KiB
C
#ifndef _S390_TLB_H
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#define _S390_TLB_H
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/*
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* TLB flushing on s390 is complicated. The following requirement
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* from the principles of operation is the most arduous:
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*
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* "A valid table entry must not be changed while it is attached
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* to any CPU and may be used for translation by that CPU except to
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* (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
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* or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
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* table entry, or (3) make a change by means of a COMPARE AND SWAP
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* AND PURGE instruction that purges the TLB."
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*
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* The modification of a pte of an active mm struct therefore is
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* a two step process: i) invalidate the pte, ii) store the new pte.
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* This is true for the page protection bit as well.
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* The only possible optimization is to flush at the beginning of
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* a tlb_gather_mmu cycle if the mm_struct is currently not in use.
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*
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* Pages used for the page tables is a different story. FIXME: more
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*/
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <linux/swap.h>
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#include <asm/processor.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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struct mmu_gather {
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struct mm_struct *mm;
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struct mmu_table_batch *batch;
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unsigned int fullmm;
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unsigned long start, unsigned long end;
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};
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struct mmu_table_batch {
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struct rcu_head rcu;
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unsigned int nr;
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void *tables[0];
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};
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#define MAX_TABLE_BATCH \
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((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *))
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extern void tlb_table_flush(struct mmu_gather *tlb);
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extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
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static inline void tlb_gather_mmu(struct mmu_gather *tlb,
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struct mm_struct *mm,
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unsigned long start,
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unsigned long end)
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{
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tlb->mm = mm;
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tlb->start = start;
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tlb->end = end;
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tlb->fullmm = !(start | (end+1));
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tlb->batch = NULL;
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if (tlb->fullmm)
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__tlb_flush_mm(mm);
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}
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static inline void tlb_flush_mmu(struct mmu_gather *tlb)
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{
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tlb_table_flush(tlb);
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}
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static inline void tlb_finish_mmu(struct mmu_gather *tlb,
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unsigned long start, unsigned long end)
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{
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tlb_table_flush(tlb);
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}
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/*
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* Release the page cache reference for a pte removed by
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* tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
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* has already been freed, so just do free_page_and_swap_cache.
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*/
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static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
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{
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free_page_and_swap_cache(page);
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return 1; /* avoid calling tlb_flush_mmu */
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}
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static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
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{
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free_page_and_swap_cache(page);
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}
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/*
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* pte_free_tlb frees a pte table and clears the CRSTE for the
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* page table from the tlb.
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*/
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static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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unsigned long address)
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{
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if (!tlb->fullmm)
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return page_table_free_rcu(tlb, (unsigned long *) pte);
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page_table_free(tlb->mm, (unsigned long *) pte);
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}
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/*
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* pmd_free_tlb frees a pmd table and clears the CRSTE for the
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* segment table entry from the tlb.
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* If the mm uses a two level page table the single pmd is freed
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* as the pgd. pmd_free_tlb checks the asce_limit against 2GB
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* to avoid the double free of the pmd in this case.
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*/
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static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
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unsigned long address)
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{
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#ifdef CONFIG_64BIT
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if (tlb->mm->context.asce_limit <= (1UL << 31))
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return;
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if (!tlb->fullmm)
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return tlb_remove_table(tlb, pmd);
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crst_table_free(tlb->mm, (unsigned long *) pmd);
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#endif
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}
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/*
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* pud_free_tlb frees a pud table and clears the CRSTE for the
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* region third table entry from the tlb.
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* If the mm uses a three level page table the single pud is freed
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* as the pgd. pud_free_tlb checks the asce_limit against 4TB
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* to avoid the double free of the pud in this case.
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*/
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static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
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unsigned long address)
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{
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#ifdef CONFIG_64BIT
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if (tlb->mm->context.asce_limit <= (1UL << 42))
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return;
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if (!tlb->fullmm)
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return tlb_remove_table(tlb, pud);
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crst_table_free(tlb->mm, (unsigned long *) pud);
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#endif
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}
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0)
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#define tlb_remove_pmd_tlb_entry(tlb, pmdp, addr) do { } while (0)
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#define tlb_migrate_finish(mm) do { } while (0)
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#endif /* _S390_TLB_H */
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