forked from Minki/linux
2995a10002
Create the sections describing the McBSP ports to be able to use them via DT. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
361 lines
7.7 KiB
Plaintext
361 lines
7.7 KiB
Plaintext
/*
|
|
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
/*
|
|
* Carveout for multimedia usecases
|
|
* It should be the last 48MB of the first 512MB memory part
|
|
* In theory, it should not even exist. That zone should be reserved
|
|
* dynamically during the .reserve callback.
|
|
*/
|
|
/memreserve/ 0x9d000000 0x03000000;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "ti,omap4430", "ti,omap4";
|
|
interrupt-parent = <&gic>;
|
|
|
|
aliases {
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
};
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
};
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@48241000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x48241000 0x1000>,
|
|
<0x48240100 0x0100>;
|
|
};
|
|
|
|
L2: l2-cache-controller@48242000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x48242000 0x1000>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
local-timer@0x48240600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x48240600 0x20>;
|
|
interrupts = <1 13 0x304>;
|
|
};
|
|
|
|
/*
|
|
* The soc node represents the soc top level view. It is uses for IPs
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
|
*/
|
|
soc {
|
|
compatible = "ti,omap-infra";
|
|
mpu {
|
|
compatible = "ti,omap4-mpu";
|
|
ti,hwmods = "mpu";
|
|
};
|
|
|
|
dsp {
|
|
compatible = "ti,omap3-c64";
|
|
ti,hwmods = "dsp";
|
|
};
|
|
|
|
iva {
|
|
compatible = "ti,ivahd";
|
|
ti,hwmods = "iva";
|
|
};
|
|
};
|
|
|
|
/*
|
|
* XXX: Use a flat representation of the OMAP4 interconnect.
|
|
* The real OMAP interconnect network is quite complex.
|
|
* Since that will not bring real advantage to represent that in DT for
|
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
|
* hierarchy.
|
|
*/
|
|
ocp {
|
|
compatible = "ti,omap4-l3-noc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
|
|
|
gpio1: gpio@4a310000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio1";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio2: gpio@48055000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio2";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio3: gpio@48057000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio3";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio4: gpio@48059000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio4";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio5: gpio@4805b000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio5";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio6: gpio@4805d000 {
|
|
compatible = "ti,omap4-gpio";
|
|
ti,hwmods = "gpio6";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
uart1: serial@4806a000 {
|
|
compatible = "ti,omap4-uart";
|
|
ti,hwmods = "uart1";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart2: serial@4806c000 {
|
|
compatible = "ti,omap4-uart";
|
|
ti,hwmods = "uart2";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart3: serial@48020000 {
|
|
compatible = "ti,omap4-uart";
|
|
ti,hwmods = "uart3";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart4: serial@4806e000 {
|
|
compatible = "ti,omap4-uart";
|
|
ti,hwmods = "uart4";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
i2c1: i2c@48070000 {
|
|
compatible = "ti,omap4-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c1";
|
|
};
|
|
|
|
i2c2: i2c@48072000 {
|
|
compatible = "ti,omap4-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c2";
|
|
};
|
|
|
|
i2c3: i2c@48060000 {
|
|
compatible = "ti,omap4-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c3";
|
|
};
|
|
|
|
i2c4: i2c@48350000 {
|
|
compatible = "ti,omap4-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c4";
|
|
};
|
|
|
|
mcspi1: spi@48098000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi1";
|
|
ti,spi-num-cs = <4>;
|
|
};
|
|
|
|
mcspi2: spi@4809a000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi2";
|
|
ti,spi-num-cs = <2>;
|
|
};
|
|
|
|
mcspi3: spi@480b8000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi3";
|
|
ti,spi-num-cs = <2>;
|
|
};
|
|
|
|
mcspi4: spi@480ba000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi4";
|
|
ti,spi-num-cs = <1>;
|
|
};
|
|
|
|
mmc1: mmc@4809c000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,hwmods = "mmc1";
|
|
ti,dual-volt;
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc2: mmc@480b4000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,hwmods = "mmc2";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc3: mmc@480ad000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,hwmods = "mmc3";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc4: mmc@480d1000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,hwmods = "mmc4";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc5: mmc@480d5000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,hwmods = "mmc5";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
wdt2: wdt@4a314000 {
|
|
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
|
|
ti,hwmods = "wd_timer2";
|
|
};
|
|
|
|
mcpdm: mcpdm@40132000 {
|
|
compatible = "ti,omap4-mcpdm";
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
interrupts = <0 112 0x4>;
|
|
interrupt-parent = <&gic>;
|
|
ti,hwmods = "mcpdm";
|
|
};
|
|
|
|
dmic: dmic@4012e000 {
|
|
compatible = "ti,omap4-dmic";
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
interrupts = <0 114 0x4>;
|
|
interrupt-parent = <&gic>;
|
|
ti,hwmods = "dmic";
|
|
};
|
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 17 0x4>;
|
|
interrupt-names = "common";
|
|
interrupt-parent = <&gic>;
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp1";
|
|
};
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 22 0x4>;
|
|
interrupt-names = "common";
|
|
interrupt-parent = <&gic>;
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp2";
|
|
};
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 23 0x4>;
|
|
interrupt-names = "common";
|
|
interrupt-parent = <&gic>;
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp3";
|
|
};
|
|
|
|
mcbsp4: mcbsp@48096000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x48096000 0xff>; /* L4 Interconnect */
|
|
reg-names = "mpu";
|
|
interrupts = <0 16 0x4>;
|
|
interrupt-names = "common";
|
|
interrupt-parent = <&gic>;
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp4";
|
|
};
|
|
|
|
keypad: keypad@4a31c000 {
|
|
compatible = "ti,omap4-keypad";
|
|
ti,hwmods = "kbd";
|
|
};
|
|
|
|
emif1: emif@4c000000 {
|
|
compatible = "ti,emif-4d";
|
|
ti,hwmods = "emif1";
|
|
phy-type = <1>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
|
|
emif2: emif@4d000000 {
|
|
compatible = "ti,emif-4d";
|
|
ti,hwmods = "emif2";
|
|
phy-type = <1>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
};
|
|
};
|