Leo (Hanghong) Ma 28fa24ad14 drm/amd/display: Change the delay time before enabling FEC ... [why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-05 18:18:33 -05:00
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amdgpu_dm	drm/amd/display: add default clocks if not able to fetch them	2019-11-26 12:19:08 -05:00
dc	drm/amd/display: Change the delay time before enabling FEC	2019-12-05 18:18:33 -05:00
include	drm/amd/display: add new active dongle to existent w/a	2019-10-10 19:33:37 -05:00
modules	drm/amd/display: Only use EETF when maxCL > max display	2019-10-25 16:50:09 -04:00
Kconfig	drm/amd: Fix Kconfig indentation	2019-10-07 15:11:17 -05:00
Makefile	drm/amd/display: Add HDCP module	2019-10-03 09:10:58 -05:00
TODO