25d316989e
The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
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| .. | ||
| bindings | ||
| booting-without-of.txt | ||
| changesets.txt | ||
| dynamic-resolution-notes.txt | ||
| of_unittest.txt | ||
| overlay-notes.txt | ||
| usage-model.txt | ||
| writing-schema.rst | ||