forked from Minki/linux
e6900ddf61
Adding EMIF device tree data for OMAP5 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
501 lines
11 KiB
Plaintext
501 lines
11 KiB
Plaintext
/*
|
|
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
* Based on "omap4.dtsi"
|
|
*/
|
|
|
|
/*
|
|
* Carveout for multimedia usecases
|
|
* It should be the last 48MB of the first 512MB memory part
|
|
* In theory, it should not even exist. That zone should be reserved
|
|
* dynamically during the .reserve callback.
|
|
*/
|
|
/memreserve/ 0x9d000000 0x03000000;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "ti,omap5";
|
|
interrupt-parent = <&gic>;
|
|
|
|
aliases {
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
serial5 = &uart6;
|
|
};
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a15";
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
/* 14th PPI IRQ, active low level-sensitive */
|
|
interrupts = <1 14 0x308>;
|
|
clock-frequency = <6144000>;
|
|
};
|
|
};
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a15";
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
/* 14th PPI IRQ, active low level-sensitive */
|
|
interrupts = <1 14 0x308>;
|
|
clock-frequency = <6144000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* The soc node represents the soc top level view. It is uses for IPs
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
|
*/
|
|
soc {
|
|
compatible = "ti,omap-infra";
|
|
mpu {
|
|
compatible = "ti,omap5-mpu";
|
|
ti,hwmods = "mpu";
|
|
};
|
|
};
|
|
|
|
/*
|
|
* XXX: Use a flat representation of the OMAP3 interconnect.
|
|
* The real OMAP interconnect network is quite complex.
|
|
* Since that will not bring real advantage to represent that in DT for
|
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
|
* hierarchy.
|
|
*/
|
|
ocp {
|
|
compatible = "ti,omap4-l3-noc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
|
|
|
counter32k: counter@4ae04000 {
|
|
compatible = "ti,omap-counter32k";
|
|
reg = <0x4ae04000 0x40>;
|
|
ti,hwmods = "counter_32k";
|
|
};
|
|
|
|
omap5_pmx_core: pinmux@4a002840 {
|
|
compatible = "ti,omap4-padconf", "pinctrl-single";
|
|
reg = <0x4a002840 0x01b6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-single,register-width = <16>;
|
|
pinctrl-single,function-mask = <0x7fff>;
|
|
};
|
|
omap5_pmx_wkup: pinmux@4ae0c840 {
|
|
compatible = "ti,omap4-padconf", "pinctrl-single";
|
|
reg = <0x4ae0c840 0x0038>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-single,register-width = <16>;
|
|
pinctrl-single,function-mask = <0x7fff>;
|
|
};
|
|
|
|
gic: interrupt-controller@48211000 {
|
|
compatible = "arm,cortex-a15-gic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x48211000 0x1000>,
|
|
<0x48212000 0x1000>;
|
|
};
|
|
|
|
gpio1: gpio@4ae10000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x4ae10000 0x200>;
|
|
interrupts = <0 29 0x4>;
|
|
ti,hwmods = "gpio1";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio2: gpio@48055000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x48055000 0x200>;
|
|
interrupts = <0 30 0x4>;
|
|
ti,hwmods = "gpio2";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio3: gpio@48057000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x48057000 0x200>;
|
|
interrupts = <0 31 0x4>;
|
|
ti,hwmods = "gpio3";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio4: gpio@48059000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x48059000 0x200>;
|
|
interrupts = <0 32 0x4>;
|
|
ti,hwmods = "gpio4";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio5: gpio@4805b000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x4805b000 0x200>;
|
|
interrupts = <0 33 0x4>;
|
|
ti,hwmods = "gpio5";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio6: gpio@4805d000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x4805d000 0x200>;
|
|
interrupts = <0 34 0x4>;
|
|
ti,hwmods = "gpio6";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio7: gpio@48051000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x48051000 0x200>;
|
|
interrupts = <0 35 0x4>;
|
|
ti,hwmods = "gpio7";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
gpio8: gpio@48053000 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x48053000 0x200>;
|
|
interrupts = <0 121 0x4>;
|
|
ti,hwmods = "gpio8";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
i2c1: i2c@48070000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x48070000 0x100>;
|
|
interrupts = <0 56 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c1";
|
|
};
|
|
|
|
i2c2: i2c@48072000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x48072000 0x100>;
|
|
interrupts = <0 57 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c2";
|
|
};
|
|
|
|
i2c3: i2c@48060000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x48060000 0x100>;
|
|
interrupts = <0 61 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c3";
|
|
};
|
|
|
|
i2c4: i2c@4807a000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x4807a000 0x100>;
|
|
interrupts = <0 62 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c4";
|
|
};
|
|
|
|
i2c5: i2c@4807c000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x4807c000 0x100>;
|
|
interrupts = <0 60 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c5";
|
|
};
|
|
|
|
uart1: serial@4806a000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x4806a000 0x100>;
|
|
interrupts = <0 72 0x4>;
|
|
ti,hwmods = "uart1";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart2: serial@4806c000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x4806c000 0x100>;
|
|
interrupts = <0 73 0x4>;
|
|
ti,hwmods = "uart2";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart3: serial@48020000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x48020000 0x100>;
|
|
interrupts = <0 74 0x4>;
|
|
ti,hwmods = "uart3";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart4: serial@4806e000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x4806e000 0x100>;
|
|
interrupts = <0 70 0x4>;
|
|
ti,hwmods = "uart4";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart5: serial@48066000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x48066000 0x100>;
|
|
interrupts = <0 105 0x4>;
|
|
ti,hwmods = "uart5";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart6: serial@48068000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x48068000 0x100>;
|
|
interrupts = <0 106 0x4>;
|
|
ti,hwmods = "uart6";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
mmc1: mmc@4809c000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x4809c000 0x400>;
|
|
interrupts = <0 83 0x4>;
|
|
ti,hwmods = "mmc1";
|
|
ti,dual-volt;
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc2: mmc@480b4000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480b4000 0x400>;
|
|
interrupts = <0 86 0x4>;
|
|
ti,hwmods = "mmc2";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc3: mmc@480ad000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480ad000 0x400>;
|
|
interrupts = <0 94 0x4>;
|
|
ti,hwmods = "mmc3";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc4: mmc@480d1000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480d1000 0x400>;
|
|
interrupts = <0 96 0x4>;
|
|
ti,hwmods = "mmc4";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
mmc5: mmc@480d5000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480d5000 0x400>;
|
|
interrupts = <0 59 0x4>;
|
|
ti,hwmods = "mmc5";
|
|
ti,needs-special-reset;
|
|
};
|
|
|
|
keypad: keypad@4ae1c000 {
|
|
compatible = "ti,omap4-keypad";
|
|
ti,hwmods = "kbd";
|
|
};
|
|
|
|
mcpdm: mcpdm@40132000 {
|
|
compatible = "ti,omap4-mcpdm";
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 112 0x4>;
|
|
ti,hwmods = "mcpdm";
|
|
};
|
|
|
|
dmic: dmic@4012e000 {
|
|
compatible = "ti,omap4-dmic";
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 114 0x4>;
|
|
ti,hwmods = "dmic";
|
|
};
|
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 17 0x4>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp1";
|
|
};
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 22 0x4>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp2";
|
|
};
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <0 23 0x4>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp3";
|
|
};
|
|
|
|
timer1: timer@4ae18000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4ae18000 0x80>;
|
|
interrupts = <0 37 0x4>;
|
|
ti,hwmods = "timer1";
|
|
ti,timer-alwon;
|
|
};
|
|
|
|
timer2: timer@48032000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48032000 0x80>;
|
|
interrupts = <0 38 0x4>;
|
|
ti,hwmods = "timer2";
|
|
};
|
|
|
|
timer3: timer@48034000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48034000 0x80>;
|
|
interrupts = <0 39 0x4>;
|
|
ti,hwmods = "timer3";
|
|
};
|
|
|
|
timer4: timer@48036000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48036000 0x80>;
|
|
interrupts = <0 40 0x4>;
|
|
ti,hwmods = "timer4";
|
|
};
|
|
|
|
timer5: timer@40138000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x40138000 0x80>,
|
|
<0x49038000 0x80>;
|
|
interrupts = <0 41 0x4>;
|
|
ti,hwmods = "timer5";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer6: timer@4013a000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4013a000 0x80>,
|
|
<0x4903a000 0x80>;
|
|
interrupts = <0 42 0x4>;
|
|
ti,hwmods = "timer6";
|
|
ti,timer-dsp;
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer7: timer@4013c000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4013c000 0x80>,
|
|
<0x4903c000 0x80>;
|
|
interrupts = <0 43 0x4>;
|
|
ti,hwmods = "timer7";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer8: timer@4013e000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4013e000 0x80>,
|
|
<0x4903e000 0x80>;
|
|
interrupts = <0 44 0x4>;
|
|
ti,hwmods = "timer8";
|
|
ti,timer-dsp;
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer9: timer@4803e000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x4803e000 0x80>;
|
|
interrupts = <0 45 0x4>;
|
|
ti,hwmods = "timer9";
|
|
};
|
|
|
|
timer10: timer@48086000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48086000 0x80>;
|
|
interrupts = <0 46 0x4>;
|
|
ti,hwmods = "timer10";
|
|
};
|
|
|
|
timer11: timer@48088000 {
|
|
compatible = "ti,omap2-timer";
|
|
reg = <0x48088000 0x80>;
|
|
interrupts = <0 47 0x4>;
|
|
ti,hwmods = "timer11";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
emif1: emif@0x4c000000 {
|
|
compatible = "ti,emif-4d5";
|
|
ti,hwmods = "emif1";
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
reg = <0x4c000000 0x400>;
|
|
interrupts = <0 110 0x4>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
|
|
emif2: emif@0x4d000000 {
|
|
compatible = "ti,emif-4d5";
|
|
ti,hwmods = "emif2";
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
reg = <0x4d000000 0x400>;
|
|
interrupts = <0 111 0x4>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
};
|
|
};
|