335aca5f65
From Nick's cover letter:
Linux powerpc new system call instruction and ABI
System Call Vectored (scv) ABI
==============================
The scv instruction is introduced with POWER9 / ISA3, it comes with an
rfscv counter-part. The benefit of these instructions is
performance (trading slower SRR0/1 with faster LR/CTR registers, and
entering the kernel with MSR[EE] and MSR[RI] left enabled, which can
reduce MSR updates. The scv instruction has 128 levels (not enough to
cover the Linux system call space).
Assignment and advertisement
----------------------------
The proposal is to assign scv levels conservatively, and advertise
them with HWCAP feature bits as we add support for more.
Linux has not enabled FSCR[SCV] yet, so executing the scv instruction
will cause the kernel to log a "SCV facility unavilable" message, and
deliver a SIGILL with ILL_ILLOPC to the process. Linux has defined a
HWCAP2 bit PPC_FEATURE2_SCV for SCV support, but does not set it.
This change allocates the zero level ('scv 0'), advertised with
PPC_FEATURE2_SCV, which will be used to provide normal Linux system
calls (equivalent to 'sc').
Attempting to execute scv with other levels will cause a SIGILL to be
delivered the same as before, but will not log a "SCV facility
unavailable" message (because the processor facility is enabled).
Calling convention
------------------
The proposal is for scv 0 to provide the standard Linux system call
ABI with the following differences from sc convention[1]:
- LR is to be volatile across scv calls. This is necessary because the
scv instruction clobbers LR. From previous discussion, this should
be possible to deal with in GCC clobbers and CFI.
- cr1 and cr5-cr7 are volatile. This matches the C ABI and would allow
the kernel system call exit to avoid restoring the volatile cr
registers (although we probably still would anyway to avoid
information leaks).
- Error handling: The consensus among kernel, glibc, and musl is to
move to using negative return values in r3 rather than CR0[SO]=1 to
indicate error, which matches most other architectures, and is
closer to a function call.
Notes
-----
- r0,r4-r8 are documented as volatile in the ABI, but the kernel patch
as submitted currently preserves them. This is to leave room for
deciding which way to go with these. Some small benefit was found by
preserving them[1] but I'm not convinced it's worth deviating from
the C function call ABI just for this. Release code should follow
the ABI.
Previous discussions:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/208691.html
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209268.html
[1] https://github.com/torvalds/linux/blob/master/Documentation/powerpc/syscall64-abi.rst
[2] https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209263.html
143 lines
3.5 KiB
C
143 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_POWERPC_EXCEPTION_H
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#define _ASM_POWERPC_EXCEPTION_H
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/*
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* Extracted from head_64.S
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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* This file contains the low-level support and setup for the
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* PowerPC-64 platform, including trap and interrupt dispatch.
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*/
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/*
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* The following macros define the code that appears as
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* the prologue to each of the exception handlers. They
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* are split into two parts to allow a single kernel binary
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* to be used for pSeries and iSeries.
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*
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* We make as much of the exception code common between native
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* exception handlers (including pSeries LPAR) and iSeries LPAR
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* implementations as possible.
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*/
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#include <asm/feature-fixups.h>
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/* PACA save area size in u64 units (exgen, exmc, etc) */
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#define EX_SIZE 10
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/*
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* maximum recursive depth of MCE exceptions
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*/
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#define MAX_MCE_DEPTH 4
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#ifdef __ASSEMBLY__
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#define STF_ENTRY_BARRIER_SLOT \
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STF_ENTRY_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define STF_EXIT_BARRIER_SLOT \
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STF_EXIT_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop
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/*
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* r10 must be free to use, r13 must be paca
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*/
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#define INTERRUPT_TO_KERNEL \
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STF_ENTRY_BARRIER_SLOT
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/*
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* Macros for annotating the expected destination of (h)rfid
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*
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* The nop instructions allow us to insert one or more instructions to flush the
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* L1-D cache when returning to userspace or a guest.
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*
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* powerpc relies on return from interrupt/syscall being context synchronising
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* (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE
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* without additional synchronisation instructions.
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*
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* soft-masked interrupt replay does not include a context-synchronising rfid,
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* but those always return to kernel, the sync is only required when returning
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* to user.
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*/
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#define RFI_FLUSH_SLOT \
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RFI_FLUSH_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define RFI_TO_KERNEL \
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rfid
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#define RFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define HRFI_TO_KERNEL \
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hrfid
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#define HRFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_UNKNOWN \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define RFSCV_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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RFSCV; \
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b rfscv_flush_fallback
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_EXCEPTION_H */
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