284aabb0e8
Add ADE display controller binding doc. Add DesignWare DSI Host Controller v1.20a binding doc. v8: None. v7: Acked by Rob Herring. v6: - Cleanup values part of reg and clocks properties. - Change "pclk_dsi" clock name to "pclk". v5: - Remove endpoint unit address of dsi output port. - Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon. - Add "resets" property for ADE reset. v4: - Describe more specific of clocks and ports. - Fix indentation. v3: - Make ade as the drm master node. - Use assigned-clocks to set clock rate. - Use ports to connect display relavant nodes. v2: - Move dt binding docs to bindings/display/hisilicon directory. Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org>
65 lines
2.3 KiB
Plaintext
65 lines
2.3 KiB
Plaintext
Device-Tree bindings for hisilicon ADE display controller driver
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ADE (Advanced Display Engine) is the display controller which grab image
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data from memory, do composition, do post image processing, generate RGB
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timing stream and transfer to DSI.
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Required properties:
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- compatible: value should be "hisilicon,hi6220-ade".
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- reg: physical base address and length of the ADE controller's registers.
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- hisilicon,noc-syscon: ADE NOC QoS syscon.
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- resets: The ADE reset controller node.
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- interrupt: the ldi vblank interrupt number used.
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- clocks: a list of phandle + clock-specifier pairs, one for each entry
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in clock-names.
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- clock-names: should contain:
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"clk_ade_core" for the ADE core clock.
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"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
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jpeg codec.
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"clk_ade_pix" for the ADE pixel clok.
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- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
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phandle + clock-specifier pairs.
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- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
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The rate of "clk_ade_core" could be "360000000" or "180000000";
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The rate of "clk_codec_jpeg" could be or less than "1440000000".
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These rate values could be configured according to performance and power
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consumption.
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- port: the output port. This contains one endpoint subnode, with its
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remote-endpoint set to the phandle of the connected DSI input endpoint.
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See Documentation/devicetree/bindings/graph.txt for more device graph info.
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Optional properties:
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- dma-coherent: Present if dma operations are coherent.
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A example of HiKey board hi6220 SoC specific DT entry:
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Example:
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ade: ade@f4100000 {
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compatible = "hisilicon,hi6220-ade";
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reg = <0x0 0xf4100000 0x0 0x7800>;
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reg-names = "ade_base";
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hisilicon,noc-syscon = <&medianoc_ade>;
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resets = <&media_ctrl MEDIA_ADE>;
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interrupts = <0 115 4>; /* ldi interrupt */
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clocks = <&media_ctrl HI6220_ADE_CORE>,
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<&media_ctrl HI6220_CODEC_JPEG>,
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<&media_ctrl HI6220_ADE_PIX_SRC>;
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/*clock name*/
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clock-names = "clk_ade_core",
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"clk_codec_jpeg",
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"clk_ade_pix";
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assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
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<&media_ctrl HI6220_CODEC_JPEG>;
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assigned-clock-rates = <360000000>, <288000000>;
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dma-coherent;
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port {
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ade_out: endpoint {
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remote-endpoint = <&dsi_in>;
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};
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};
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};
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