e2fb373038
Unlike earlier silicon variants, OcteonTx2 98xx silicon has 2 NIX blocks and each of the CGX is mapped to either of the NIX blocks. Each NIX block supports 100G. Mapping btw NIX blocks and CGX is done by firmware based on CGX speed config to have a maximum possible network bandwidth. Since the mapping is not fixed, it's difficult for a user to figure out. Hence added a debugfs entry which displays mapping between CGX LMAC, NIX block and RVU PF. Sample result of this entry :: ~# cat /sys/kernel/debug/octeontx2/rvu_pf_cgx_map PCI dev RVU PF Func NIX block CGX LMAC 0002:02:00.0 0x400 NIX0 CGX0 LMAC0 Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
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| .. | ||
| mvpp2 | ||
| octeontx2 | ||
| prestera | ||
| Kconfig | ||
| Makefile | ||
| mv643xx_eth.c | ||
| mvmdio.c | ||
| mvneta_bm.c | ||
| mvneta_bm.h | ||
| mvneta.c | ||
| pxa168_eth.c | ||
| skge.c | ||
| skge.h | ||
| sky2.c | ||
| sky2.h | ||