Konrad Dybcio 00fd44a1a4 drm/msm: Only enable A6xx LLCC code on A6xx ...

Using this code on A5xx (and probably older too) causes a
smmu bug.

Fixes: 474dadb8b0 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

2021-01-07 09:23:05 -08:00

..

a2xx_gpu.c

drm/msm: Add modparam to allow vram carveout

2021-01-07 09:12:53 -08:00

a2xx_gpu.h

drm/msm/adreno: add a2xx

2018-12-11 13:07:06 -05:00

a2xx.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

a3xx_gpu.c

drm/msm: Add modparam to allow vram carveout

2021-01-07 09:12:53 -08:00

a3xx_gpu.h

drm/msm/gpu: add ocmem init/cleanup functions

2019-10-07 08:17:39 -07:00

a3xx.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

a4xx_gpu.c

drm/msm: Add modparam to allow vram carveout

2021-01-07 09:12:53 -08:00

a4xx_gpu.h

drm/msm/gpu: add ocmem init/cleanup functions

2019-10-07 08:17:39 -07:00

a4xx.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

a5xx_debugfs.c

drm/msm/adreno: remove return value of function XX_print

2020-09-04 12:15:30 -07:00

a5xx_gpu.c

drm/msm: a5xx: Make preemption reset case reentrant

2020-12-05 08:19:15 -08:00

a5xx_gpu.h

drm/msm: Allow a5xx to mark the RPTR shadow as privileged

2020-09-15 10:47:44 -07:00

a5xx_power.c

drm/msm: Allow a5xx to mark the RPTR shadow as privileged

2020-09-15 10:47:44 -07:00

a5xx_preempt.c

drm/msm: Document and rename preempt_lock

2020-11-04 16:00:56 -08:00

a5xx.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

a6xx_gmu.c

drm/msm/gpu: Convert retire/recover work to kthread_worker

2020-11-01 10:13:32 -08:00

a6xx_gmu.h

drm/msm/a6xx: fix crashstate capture for A650

2020-07-31 06:46:16 -07:00

a6xx_gmu.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

a6xx_gpu_state.c

drm/msm/adreno/a6xx_gpu_state: Make some local functions static

2020-11-29 10:36:53 -08:00

a6xx_gpu_state.h

drm/msm/a6xx: fix crashdec section name typo

2020-08-22 10:36:30 -07:00

a6xx_gpu.c

drm/msm/a6xx: Add support for using system cache on MMU500 based targets

2020-11-29 11:04:06 -08:00

a6xx_gpu.h

drm/msm/a6xx: Add support for using system cache on MMU500 based targets

2020-11-29 11:04:06 -08:00

a6xx_hfi.c

drm/msm/a6xx: add build_bw_table for A640/A650

2020-07-31 06:46:16 -07:00

a6xx_hfi.h

drm/msm/a6xx: HFI v2 for A640 and A650

2020-05-18 09:26:33 -07:00

a6xx.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

adreno_common.xml.h

drm/msm: sync generated headers

2020-07-31 06:46:16 -07:00

adreno_device.c

drm/msm: Add modparam to allow vram carveout

2021-01-07 09:12:53 -08:00

adreno_gpu.c

drm/msm: Only enable A6xx LLCC code on A6xx

2021-01-07 09:23:05 -08:00

adreno_gpu.h

drm/msm: Only enable A6xx LLCC code on A6xx

2021-01-07 09:23:05 -08:00

adreno_pm4.xml.h

drm/msm: Allow a5xx to mark the RPTR shadow as privileged

2020-09-15 10:47:44 -07:00