linux/drivers/gpu
Imre Deak 1af474fef2 drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
Although on HSW/BDW there is only a single display global power well,
it's programmed the same way as other GEN9+ power wells. This also
means we can get at the HSW/BDW request and status flags the same way
it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID.
This ID was assigned in a recent patch, so we can now switch to using
the same macros everywhere on HSW+.

Updating the HSW power well control register with RMW is not strictly
necessary, but this will allow us to use the same code for GEN9+.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-13-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-07-27 09:38:52 +02:00
..
drm drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros 2017-07-27 09:38:52 +02:00
host1x Linux 4.12-rc7 2017-06-27 08:28:30 +10:00
ipu-v3 drm: Convert to using %pOF instead of full_name 2017-07-26 13:45:06 +02:00
vga sched/wait: Rename wait_queue_t => wait_queue_entry_t 2017-06-20 12:18:27 +02:00
Makefile