1abb081e41
The Tegra194 BPMP only implements 5 channels (4 to BPMP, 1 to CCPLEX), and they are not placed contiguously in memory. The current channel management in the BPMP driver does not support this. Simplify and refactor the channel management such that only one atomic transmit channel and one receive channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| arc | ||
| at91 | ||
| bcm2835 | ||
| brcmstb | ||
| fsl | ||
| imx | ||
| mediatek | ||
| nps | ||
| rockchip | ||
| sa1100 | ||
| tegra | ||