Kan Liang 1aaccc40a1 perf/x86/msr: Add missing CPU IDs ... Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well. Signed-off-by: Kan Liang <Kan.liang@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: ak@linux.intel.com Cc: peterz@infradead.org Cc: piotr.luc@intel.com Cc: harry.pan@intel.com Cc: srinivas.pandruvada@linux.intel.com Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com		2017-09-25 09:36:17 +02:00
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amd	perf/x86/amd/uncore: Get correct number of cores sharing last level cache	2017-08-10 12:08:39 +02:00
intel	perf/x86/intel/cstate: Add missing CPU IDs	2017-09-25 09:36:17 +02:00
core.c	Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2017-09-04 08:39:02 -07:00
Kconfig	perf/x86: Move Kconfig.perf and other perf configuration bits to events/Kconfig	2016-03-31 10:30:40 +02:00
Makefile	perf/x86/events: Add an AMD-specific Makefile	2017-01-30 12:01:19 +01:00
msr.c	perf/x86/msr: Add missing CPU IDs	2017-09-25 09:36:17 +02:00
perf_event.h	perf/core, x86: Add PERF_SAMPLE_PHYS_ADDR	2017-08-29 15:09:25 +02:00