18c71ce9c8
Update the CPU features to include identifying and reporting on the Secure Encrypted Virtualization (SEV) feature. SEV is identified by CPUID 0x8000001f, but requires BIOS support to enable it (set bit 23 of MSR_K8_SYSCFG and set bit 0 of MSR_K7_HWCR). Only show the SEV feature as available if reported by CPUID and enabled by BIOS. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Borislav Petkov <bp@suse.de> Cc: kvm@vger.kernel.org Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Borislav Petkov <bp@suse.de>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/*
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* Routines to identify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/pat.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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u32 sub_leaf;
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};
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/* Please keep the leaf sorted by cpuid_bit.level for faster search. */
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static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
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{ X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
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{ X86_FEATURE_INTEL_PT, CPUID_EBX, 25, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 },
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{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
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{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
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{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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{ X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
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{ X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
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®s[CPUID_EBX], ®s[CPUID_ECX],
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®s[CPUID_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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u32 get_scattered_cpuid_leaf(unsigned int level, unsigned int sub_leaf,
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enum cpuid_regs_idx reg)
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{
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const struct cpuid_bit *cb;
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u32 cpuid_val = 0;
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for (cb = cpuid_bits; cb->feature; cb++) {
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if (level > cb->level)
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continue;
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if (level < cb->level)
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break;
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if (reg == cb->reg && sub_leaf == cb->sub_leaf) {
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if (cpu_has(&boot_cpu_data, cb->feature))
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cpuid_val |= BIT(cb->bit);
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}
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}
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return cpuid_val;
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}
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EXPORT_SYMBOL_GPL(get_scattered_cpuid_leaf);
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