18c46461d9
Some firmware appears to enable interrupts during boot service calls, even if we've explicitly disabled them prior to the call. This is actually allowed per the UEFI spec because boottime services expect to be called with interrupts enabled. So that's fine, we just need to ensure that we disable them again in efi_enter32() before switching to a 64-bit GDT, otherwise an interrupt may fire causing a 32-bit IRQ handler to run after we've left compatibility mode. Despite efi_enter32() being called both for boottime and runtime services, this really only affects boottime because the runtime services callchain is executed with interrupts disabled. See efi_thunk(). Signed-off-by: Matt Fleming <matt.fleming@intel.com>
328 lines
5.3 KiB
ArmAsm
328 lines
5.3 KiB
ArmAsm
/*
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* Function calling ABI conversion from Linux to EFI for x86_64
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*
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* Copyright (C) 2007 Intel Corp
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* Bibo Mao <bibo.mao@intel.com>
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* Huang Ying <ying.huang@intel.com>
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*/
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/msr.h>
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#include <asm/processor-flags.h>
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#include <asm/page_types.h>
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#define SAVE_XMM \
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mov %rsp, %rax; \
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subq $0x70, %rsp; \
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and $~0xf, %rsp; \
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mov %rax, (%rsp); \
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mov %cr0, %rax; \
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clts; \
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mov %rax, 0x8(%rsp); \
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movaps %xmm0, 0x60(%rsp); \
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movaps %xmm1, 0x50(%rsp); \
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movaps %xmm2, 0x40(%rsp); \
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movaps %xmm3, 0x30(%rsp); \
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movaps %xmm4, 0x20(%rsp); \
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movaps %xmm5, 0x10(%rsp)
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#define RESTORE_XMM \
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movaps 0x60(%rsp), %xmm0; \
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movaps 0x50(%rsp), %xmm1; \
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movaps 0x40(%rsp), %xmm2; \
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movaps 0x30(%rsp), %xmm3; \
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movaps 0x20(%rsp), %xmm4; \
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movaps 0x10(%rsp), %xmm5; \
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mov 0x8(%rsp), %rsi; \
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mov %rsi, %cr0; \
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mov (%rsp), %rsp
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/* stolen from gcc */
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.macro FLUSH_TLB_ALL
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movq %r15, efi_scratch(%rip)
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movq %r14, efi_scratch+8(%rip)
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movq %cr4, %r15
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movq %r15, %r14
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andb $0x7f, %r14b
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movq %r14, %cr4
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movq %r15, %cr4
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movq efi_scratch+8(%rip), %r14
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movq efi_scratch(%rip), %r15
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.endm
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.macro SWITCH_PGT
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cmpb $0, efi_scratch+24(%rip)
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je 1f
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movq %r15, efi_scratch(%rip) # r15
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# save previous CR3
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movq %cr3, %r15
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movq %r15, efi_scratch+8(%rip) # prev_cr3
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movq efi_scratch+16(%rip), %r15 # EFI pgt
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movq %r15, %cr3
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1:
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.endm
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.macro RESTORE_PGT
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cmpb $0, efi_scratch+24(%rip)
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je 2f
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movq efi_scratch+8(%rip), %r15
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movq %r15, %cr3
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movq efi_scratch(%rip), %r15
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FLUSH_TLB_ALL
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2:
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.endm
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ENTRY(efi_call0)
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SAVE_XMM
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subq $32, %rsp
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $32, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call0)
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ENTRY(efi_call1)
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SAVE_XMM
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subq $32, %rsp
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $32, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call1)
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ENTRY(efi_call2)
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SAVE_XMM
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subq $32, %rsp
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $32, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call2)
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ENTRY(efi_call3)
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SAVE_XMM
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subq $32, %rsp
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mov %rcx, %r8
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $32, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call3)
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ENTRY(efi_call4)
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SAVE_XMM
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subq $32, %rsp
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mov %r8, %r9
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mov %rcx, %r8
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $32, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call4)
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ENTRY(efi_call5)
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SAVE_XMM
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subq $48, %rsp
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mov %r9, 32(%rsp)
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mov %r8, %r9
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mov %rcx, %r8
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $48, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call5)
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ENTRY(efi_call6)
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SAVE_XMM
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mov (%rsp), %rax
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mov 8(%rax), %rax
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subq $48, %rsp
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mov %r9, 32(%rsp)
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mov %rax, 40(%rsp)
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mov %r8, %r9
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mov %rcx, %r8
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mov %rsi, %rcx
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SWITCH_PGT
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call *%rdi
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RESTORE_PGT
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addq $48, %rsp
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RESTORE_XMM
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ret
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ENDPROC(efi_call6)
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#ifdef CONFIG_EFI_MIXED
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/*
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* We run this function from the 1:1 mapping.
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*
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* This function must be invoked with a 1:1 mapped stack.
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*/
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ENTRY(__efi64_thunk)
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subq $32, %rsp
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movl %esi, 0x0(%rsp)
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movl %edx, 0x4(%rsp)
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movl %ecx, 0x8(%rsp)
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movq %r8, %rsi
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movl %esi, 0xc(%rsp)
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movq %r9, %rsi
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movl %esi, 0x10(%rsp)
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sgdt save_gdt(%rip)
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leaq 1f(%rip), %rbx
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movq %rbx, func_rt_ptr(%rip)
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/* Switch to gdt with 32-bit segments */
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movl 40(%rsp), %eax
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lgdt (%rax)
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leaq efi_enter32(%rip), %rax
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pushq $__KERNEL_CS
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pushq %rax
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lretq
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1: addq $32, %rsp
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lgdt save_gdt(%rip)
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/*
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* Convert 32-bit status code into 64-bit.
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*/
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test %rax, %rax
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jz 1f
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movl %eax, %ecx
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andl $0x0fffffff, %ecx
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andl $0xf0000000, %eax
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shl $32, %rax
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or %rcx, %rax
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1:
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ret
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ENDPROC(__efi64_thunk)
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ENTRY(efi_exit32)
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xorq %rax, %rax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %ss
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movq func_rt_ptr(%rip), %rax
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push %rax
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mov %rdi, %rax
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ret
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ENDPROC(efi_exit32)
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.code32
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/*
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* EFI service pointer must be in %edi.
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*
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* The stack should represent the 32-bit calling convention.
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*/
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ENTRY(efi_enter32)
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movl $__KERNEL_DS, %eax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %ss
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/* Reload pgtables */
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movl %cr3, %eax
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movl %eax, %cr3
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/* Disable long mode via EFER */
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movl $MSR_EFER, %ecx
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rdmsr
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btrl $_EFER_LME, %eax
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wrmsr
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call *%edi
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/* We must preserve return value */
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movl %eax, %edi
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/*
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* Some firmware will return with interrupts enabled. Be sure to
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* disable them before we switch GDTs.
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*/
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cli
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movl 44(%esp), %eax
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movl %eax, 2(%eax)
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lgdtl (%eax)
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movl %cr4, %eax
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btsl $(X86_CR4_PAE_BIT), %eax
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movl %eax, %cr4
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movl %cr3, %eax
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movl %eax, %cr3
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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xorl %eax, %eax
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lldt %ax
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movl 48(%esp), %eax
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pushl $__KERNEL_CS
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pushl %eax
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/* Enable paging */
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movl %cr0, %eax
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btsl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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lret
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ENDPROC(efi_enter32)
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.data
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.balign 8
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.global efi32_boot_gdt
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efi32_boot_gdt: .word 0
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.quad 0
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save_gdt: .word 0
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.quad 0
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func_rt_ptr: .quad 0
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.global efi_gdt64
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efi_gdt64:
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.word efi_gdt64_end - efi_gdt64
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.long 0 /* Filled out by user */
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.word 0
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.quad 0x0000000000000000 /* NULL descriptor */
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.quad 0x00af9a000000ffff /* __KERNEL_CS */
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.quad 0x00cf92000000ffff /* __KERNEL_DS */
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.quad 0x0080890000000000 /* TS descriptor */
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.quad 0x0000000000000000 /* TS continued */
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efi_gdt64_end:
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#endif /* CONFIG_EFI_MIXED */
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.data
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ENTRY(efi_scratch)
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.fill 3,8,0
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.byte 0
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.quad 0
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