linux/Documentation/devicetree/bindings/powerpc/fsl
Scott Wood 180076cb11 powerpc: Add fsl mpic timer binding
Update the existing example in the general mpic binding to have a
separate TCRx region.  Currently the example doesn't describe TCRx at
all.  The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between.  That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.

Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.

Add fsl,available-ranges, similar to msi-available-ranges.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-19 01:14:25 -05:00
..
cpm_qe
board.txt
cache_sram.txt powerpc/fsl: 85xx: document cache sram bindings 2011-03-15 14:09:06 -05:00
diu.txt
dma.txt
ecm.txt
gtm.txt
guts.txt
lbc.txt
mcm.txt
mcu-mpc8349emitx.txt
mpc5121-psc.txt
mpc5200.txt
mpic-timer.txt powerpc: Add fsl mpic timer binding 2011-05-19 01:14:25 -05:00
mpic.txt powerpc: Add fsl mpic timer binding 2011-05-19 01:14:25 -05:00
msi-pic.txt powerpc/fsl_msi: Handle msi-available-ranges better 2011-03-15 13:48:16 -05:00
pmc.txt
sec.txt
ssi.txt