forked from Minki/linux
b081251ef6
Add an include of asm/smp.h to fix a build break when SMP=n:
arch/powerpc/sysdev/fsl_rcpm.c:32:2: error: implicit declaration of
function 'get_hard_smp_processor_id'
Fixes: d17799f9c1 ("powerpc/rcpm: add RCPM driver")
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
387 lines
8.7 KiB
C
387 lines
8.7 KiB
C
/*
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* RCPM(Run Control/Power Management) support
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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*
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* Author: Chenhui Zhao <chenhui.zhao@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/of_address.h>
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#include <linux/export.h>
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#include <asm/io.h>
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#include <linux/fsl/guts.h>
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#include <asm/cputhreads.h>
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#include <asm/fsl_pm.h>
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#include <asm/smp.h>
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static struct ccsr_rcpm_v1 __iomem *rcpm_v1_regs;
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static struct ccsr_rcpm_v2 __iomem *rcpm_v2_regs;
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static unsigned int fsl_supported_pm_modes;
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static void rcpm_v1_irq_mask(int cpu)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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setbits32(&rcpm_v1_regs->cpmimr, mask);
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setbits32(&rcpm_v1_regs->cpmcimr, mask);
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setbits32(&rcpm_v1_regs->cpmmcmr, mask);
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setbits32(&rcpm_v1_regs->cpmnmimr, mask);
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}
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static void rcpm_v2_irq_mask(int cpu)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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setbits32(&rcpm_v2_regs->tpmimr0, mask);
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setbits32(&rcpm_v2_regs->tpmcimr0, mask);
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setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
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setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
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}
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static void rcpm_v1_irq_unmask(int cpu)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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clrbits32(&rcpm_v1_regs->cpmimr, mask);
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clrbits32(&rcpm_v1_regs->cpmcimr, mask);
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clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
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clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
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}
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static void rcpm_v2_irq_unmask(int cpu)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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clrbits32(&rcpm_v2_regs->tpmimr0, mask);
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clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
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clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
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clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
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}
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static void rcpm_v1_set_ip_power(bool enable, u32 mask)
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{
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if (enable)
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setbits32(&rcpm_v1_regs->ippdexpcr, mask);
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else
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clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
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}
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static void rcpm_v2_set_ip_power(bool enable, u32 mask)
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{
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if (enable)
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setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
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else
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clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
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}
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static void rcpm_v1_cpu_enter_state(int cpu, int state)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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switch (state) {
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case E500_PM_PH10:
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setbits32(&rcpm_v1_regs->cdozcr, mask);
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break;
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case E500_PM_PH15:
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setbits32(&rcpm_v1_regs->cnapcr, mask);
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break;
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default:
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pr_warn("Unknown cpu PM state (%d)\n", state);
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break;
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}
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}
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static void rcpm_v2_cpu_enter_state(int cpu, int state)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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u32 mask = 1 << cpu_core_index_of_thread(cpu);
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switch (state) {
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case E500_PM_PH10:
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/* one bit corresponds to one thread for PH10 of 6500 */
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setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
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break;
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case E500_PM_PH15:
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setbits32(&rcpm_v2_regs->pcph15setr, mask);
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break;
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case E500_PM_PH20:
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setbits32(&rcpm_v2_regs->pcph20setr, mask);
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break;
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case E500_PM_PH30:
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setbits32(&rcpm_v2_regs->pcph30setr, mask);
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break;
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default:
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pr_warn("Unknown cpu PM state (%d)\n", state);
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}
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}
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static void rcpm_v1_cpu_die(int cpu)
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{
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rcpm_v1_cpu_enter_state(cpu, E500_PM_PH15);
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}
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#ifdef CONFIG_PPC64
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static void qoriq_disable_thread(int cpu)
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{
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int thread = cpu_thread_in_core(cpu);
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book3e_stop_thread(thread);
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}
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#endif
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static void rcpm_v2_cpu_die(int cpu)
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{
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#ifdef CONFIG_PPC64
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int primary;
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if (threads_per_core == 2) {
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primary = cpu_first_thread_sibling(cpu);
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if (cpu_is_offline(primary) && cpu_is_offline(primary + 1)) {
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/* if both threads are offline, put the cpu in PH20 */
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rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
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} else {
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/* if only one thread is offline, disable the thread */
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qoriq_disable_thread(cpu);
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}
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}
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#endif
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if (threads_per_core == 1)
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rcpm_v2_cpu_enter_state(cpu, E500_PM_PH20);
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}
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static void rcpm_v1_cpu_exit_state(int cpu, int state)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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unsigned int mask = 1 << hw_cpu;
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switch (state) {
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case E500_PM_PH10:
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clrbits32(&rcpm_v1_regs->cdozcr, mask);
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break;
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case E500_PM_PH15:
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clrbits32(&rcpm_v1_regs->cnapcr, mask);
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break;
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default:
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pr_warn("Unknown cpu PM state (%d)\n", state);
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break;
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}
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}
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static void rcpm_v1_cpu_up_prepare(int cpu)
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{
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rcpm_v1_cpu_exit_state(cpu, E500_PM_PH15);
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rcpm_v1_irq_unmask(cpu);
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}
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static void rcpm_v2_cpu_exit_state(int cpu, int state)
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{
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int hw_cpu = get_hard_smp_processor_id(cpu);
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u32 mask = 1 << cpu_core_index_of_thread(cpu);
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switch (state) {
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case E500_PM_PH10:
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setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
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break;
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case E500_PM_PH15:
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setbits32(&rcpm_v2_regs->pcph15clrr, mask);
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break;
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case E500_PM_PH20:
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setbits32(&rcpm_v2_regs->pcph20clrr, mask);
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break;
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case E500_PM_PH30:
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setbits32(&rcpm_v2_regs->pcph30clrr, mask);
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break;
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default:
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pr_warn("Unknown cpu PM state (%d)\n", state);
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}
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}
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static void rcpm_v2_cpu_up_prepare(int cpu)
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{
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rcpm_v2_cpu_exit_state(cpu, E500_PM_PH20);
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rcpm_v2_irq_unmask(cpu);
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}
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static int rcpm_v1_plat_enter_state(int state)
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{
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u32 *pmcsr_reg = &rcpm_v1_regs->powmgtcsr;
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int ret = 0;
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int result;
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switch (state) {
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case PLAT_PM_SLEEP:
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setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
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/* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
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result = spin_event_timeout(
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!(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_SLP), 10000, 10);
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if (!result) {
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pr_err("timeout waiting for SLP bit to be cleared\n");
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ret = -ETIMEDOUT;
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}
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break;
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default:
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pr_warn("Unknown platform PM state (%d)", state);
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ret = -EINVAL;
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}
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return ret;
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}
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static int rcpm_v2_plat_enter_state(int state)
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{
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u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;
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int ret = 0;
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int result;
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switch (state) {
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case PLAT_PM_LPM20:
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/* clear previous LPM20 status */
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setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
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/* enter LPM20 status */
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setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
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/* At this point, the device is in LPM20 status. */
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/* resume ... */
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result = spin_event_timeout(
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!(in_be32(pmcsr_reg) & RCPM_POWMGTCSR_LPM20_ST), 10000, 10);
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if (!result) {
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pr_err("timeout waiting for LPM20 bit to be cleared\n");
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ret = -ETIMEDOUT;
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}
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break;
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default:
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pr_warn("Unknown platform PM state (%d)\n", state);
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ret = -EINVAL;
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}
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return ret;
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}
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static int rcpm_v1_plat_enter_sleep(void)
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{
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return rcpm_v1_plat_enter_state(PLAT_PM_SLEEP);
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}
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static int rcpm_v2_plat_enter_sleep(void)
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{
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return rcpm_v2_plat_enter_state(PLAT_PM_LPM20);
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}
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static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
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{
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static u32 mask;
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if (freeze) {
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mask = in_be32(tben_reg);
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clrbits32(tben_reg, mask);
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} else {
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setbits32(tben_reg, mask);
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}
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/* read back to push the previous write */
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in_be32(tben_reg);
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}
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static void rcpm_v1_freeze_time_base(bool freeze)
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{
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rcpm_common_freeze_time_base(&rcpm_v1_regs->ctbenr, freeze);
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}
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static void rcpm_v2_freeze_time_base(bool freeze)
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{
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rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);
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}
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static unsigned int rcpm_get_pm_modes(void)
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{
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return fsl_supported_pm_modes;
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}
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static const struct fsl_pm_ops qoriq_rcpm_v1_ops = {
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.irq_mask = rcpm_v1_irq_mask,
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.irq_unmask = rcpm_v1_irq_unmask,
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.cpu_enter_state = rcpm_v1_cpu_enter_state,
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.cpu_exit_state = rcpm_v1_cpu_exit_state,
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.cpu_up_prepare = rcpm_v1_cpu_up_prepare,
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.cpu_die = rcpm_v1_cpu_die,
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.plat_enter_sleep = rcpm_v1_plat_enter_sleep,
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.set_ip_power = rcpm_v1_set_ip_power,
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.freeze_time_base = rcpm_v1_freeze_time_base,
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.get_pm_modes = rcpm_get_pm_modes,
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};
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static const struct fsl_pm_ops qoriq_rcpm_v2_ops = {
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.irq_mask = rcpm_v2_irq_mask,
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.irq_unmask = rcpm_v2_irq_unmask,
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.cpu_enter_state = rcpm_v2_cpu_enter_state,
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.cpu_exit_state = rcpm_v2_cpu_exit_state,
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.cpu_up_prepare = rcpm_v2_cpu_up_prepare,
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.cpu_die = rcpm_v2_cpu_die,
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.plat_enter_sleep = rcpm_v2_plat_enter_sleep,
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.set_ip_power = rcpm_v2_set_ip_power,
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.freeze_time_base = rcpm_v2_freeze_time_base,
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.get_pm_modes = rcpm_get_pm_modes,
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};
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static const struct of_device_id rcpm_matches[] = {
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{
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.compatible = "fsl,qoriq-rcpm-1.0",
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.data = &qoriq_rcpm_v1_ops,
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},
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{
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.compatible = "fsl,qoriq-rcpm-2.0",
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.data = &qoriq_rcpm_v2_ops,
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},
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{
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.compatible = "fsl,qoriq-rcpm-2.1",
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.data = &qoriq_rcpm_v2_ops,
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},
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{},
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};
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int __init fsl_rcpm_init(void)
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{
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struct device_node *np;
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const struct of_device_id *match;
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void __iomem *base;
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np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
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if (!np)
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return 0;
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base = of_iomap(np, 0);
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of_node_put(np);
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if (!base) {
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pr_err("of_iomap() error.\n");
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return -ENOMEM;
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}
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rcpm_v1_regs = base;
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rcpm_v2_regs = base;
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/* support sleep by default */
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fsl_supported_pm_modes = FSL_PM_SLEEP;
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qoriq_pm_ops = match->data;
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return 0;
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}
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