forked from Minki/linux
175f354b75
Before: total: 34 errors, 14 warnings, 456 lines checked After: total: 0 errors, 8 warnings, 456 lines checked [bart: md5sum checked] Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
457 lines
13 KiB
C
457 lines
13 KiB
C
/*
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* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
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* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
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*
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* CYPRESS CY82C693 chipset IDE controller
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*
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* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
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* Writing the driver was quite simple, since most of the job is
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* done by the generic pci-ide support.
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* The hard part was finding the CY82C693's datasheet on Cypress's
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* web page :-(. But Altavista solved this problem :-).
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*
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*
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* Notes:
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* - I recently got a 16.8G IBM DTTA, so I was able to test it with
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* a large and fast disk - the results look great, so I'd say the
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* driver is working fine :-)
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* hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
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* - this is my first linux driver, so there's probably a lot of room
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* for optimizations and bug fixing, so feel free to do it.
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* - use idebus=xx parameter to set PCI bus speed - needed to calc
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* timings for PIO modes (default will be 40)
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* - if using PIO mode it's a good idea to set the PIO mode and
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* 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
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* - I had some problems with my IBM DHEA with PIO modes < 2
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* (lost interrupts) ?????
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* - first tests with DMA look okay, they seem to work, but there is a
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* problem with sound - the BusMaster IDE TimeOut should fixed this
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*
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* Ancient History:
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* AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
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* ASK@1999-01-23: v0.33 made a few minor code clean ups
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* removed DMA clock speed setting by default
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* added boot message
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* ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
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* added support to set DMA Controller Clock Speed
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* ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
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* on some drives.
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* ASK@1998-10-29: v0.3 added support to set DMA modes
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* ASK@1998-10-28: v0.2 added support to set PIO modes
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* ASK@1998-10-27: v0.1 first version - chipset detection
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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/* the current version */
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#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
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/*
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* The following are used to debug the driver.
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*/
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#define CY82C693_DEBUG_LOGS 0
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#define CY82C693_DEBUG_INFO 0
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/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
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#undef CY82C693_SETDMA_CLOCK
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/*
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* NOTE: the value for busmaster timeout is tricky and I got it by
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* trial and error! By using a to low value will cause DMA timeouts
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* and drop IDE performance, and by using a to high value will cause
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* audio playback to scatter.
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* If you know a better value or how to calc it, please let me know.
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*/
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/* twice the value written in cy82c693ub datasheet */
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#define BUSMASTER_TIMEOUT 0x50
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/*
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* the value above was tested on my machine and it seems to work okay
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*/
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/* here are the offset definitions for the registers */
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#define CY82_IDE_CMDREG 0x04
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#define CY82_IDE_ADDRSETUP 0x48
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#define CY82_IDE_MASTER_IOR 0x4C
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#define CY82_IDE_MASTER_IOW 0x4D
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#define CY82_IDE_SLAVE_IOR 0x4E
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#define CY82_IDE_SLAVE_IOW 0x4F
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#define CY82_IDE_MASTER_8BIT 0x50
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#define CY82_IDE_SLAVE_8BIT 0x51
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#define CY82_INDEX_PORT 0x22
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#define CY82_DATA_PORT 0x23
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#define CY82_INDEX_CTRLREG1 0x01
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#define CY82_INDEX_CHANNEL0 0x30
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#define CY82_INDEX_CHANNEL1 0x31
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#define CY82_INDEX_TIMEOUT 0x32
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/* the min and max PCI bus speed in MHz - from datasheet */
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#define CY82C963_MIN_BUS_SPEED 25
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#define CY82C963_MAX_BUS_SPEED 33
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/* the struct for the PIO mode timings */
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typedef struct pio_clocks_s {
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u8 address_time; /* Address setup (clocks) */
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u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
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u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
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u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
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} pio_clocks_t;
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/*
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* calc clocks using bus_speed
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* returns (rounded up) time in bus clocks for time in ns
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*/
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static int calc_clk(int time, int bus_speed)
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{
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int clocks;
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clocks = (time*bus_speed+999)/1000 - 1;
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if (clocks < 0)
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clocks = 0;
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if (clocks > 0x0F)
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clocks = 0x0F;
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return clocks;
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}
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/*
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* compute the values for the clock registers for PIO
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* mode and pci_clk [MHz] speed
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*
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* NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
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* for mode 3 and 4 drives 8 and 16-bit timings are the same
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*
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*/
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static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
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{
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int clk1, clk2;
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int bus_speed = system_bus_clock(); /* get speed of PCI bus */
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/* we don't check against CY82C693's min and max speed,
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* so you can play with the idebus=xx parameter
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*/
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/* let's calc the address setup time clocks */
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p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
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/* let's calc the active and recovery time clocks */
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clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
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/* calc recovery timing */
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clk2 = ide_pio_timings[pio].cycle_time -
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ide_pio_timings[pio].active_time -
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ide_pio_timings[pio].setup_time;
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clk2 = calc_clk(clk2, bus_speed);
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clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
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/* note: we use the same values for 16bit IOR and IOW
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* those are all the same, since I don't have other
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* timings than those from ide-lib.c
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*/
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p_pclk->time_16r = (u8)clk1;
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p_pclk->time_16w = (u8)clk1;
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/* what are good values for 8bit ?? */
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p_pclk->time_8 = (u8)clk1;
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}
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/*
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* set DMA mode a specific channel for CY82C693
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*/
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static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
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index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
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#if CY82C693_DEBUG_LOGS
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/* for debug let's show the previous values */
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outb(index, CY82_INDEX_PORT);
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data = inb(CY82_DATA_PORT);
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printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
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drive->name, HWIF(drive)->channel, drive->select.b.unit,
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(data&0x3), ((data>>2)&1));
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#endif /* CY82C693_DEBUG_LOGS */
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data = (mode & 3) | (single << 2);
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outb(index, CY82_INDEX_PORT);
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outb(data, CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
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drive->name, HWIF(drive)->channel, drive->select.b.unit,
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mode & 3, single);
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#endif /* CY82C693_DEBUG_INFO */
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/*
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* note: below we set the value for Bus Master IDE TimeOut Register
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* I'm not absolutly sure what this does, but it solved my problem
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* with IDE DMA and sound, so I now can play sound and work with
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* my IDE driver at the same time :-)
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*
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* If you know the correct (best) value for this register please
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* let me know - ASK
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*/
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data = BUSMASTER_TIMEOUT;
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outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
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outb(data, CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
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drive->name, data);
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#endif /* CY82C693_DEBUG_INFO */
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}
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static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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pio_clocks_t pclk;
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unsigned int addrCtrl;
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/* select primary or secondary channel */
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if (hwif->index > 0) { /* drive is on the secondary channel */
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dev = pci_get_slot(dev->bus, dev->devfn+1);
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if (!dev) {
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printk(KERN_ERR "%s: tune_drive: "
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"Cannot find secondary interface!\n",
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drive->name);
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return;
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}
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}
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#if CY82C693_DEBUG_LOGS
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/* for debug let's show the register values */
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if (drive->select.b.unit == 0) {
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/*
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* get master drive registers
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* address setup control register
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* is 32 bit !!!
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*/
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pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
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addrCtrl &= 0x0F;
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/* now let's get the remaining registers */
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pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
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pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
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pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
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} else {
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/*
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* set slave drive registers
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* address setup control register
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* is 32 bit !!!
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*/
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pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
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addrCtrl &= 0xF0;
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addrCtrl >>= 4;
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/* now let's get the remaining registers */
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pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
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pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
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pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
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}
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printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
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"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
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drive->name, hwif->channel, drive->select.b.unit,
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addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
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#endif /* CY82C693_DEBUG_LOGS */
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/* let's calc the values for this PIO mode */
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compute_clocks(pio, &pclk);
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/* now let's write the clocks registers */
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if (drive->select.b.unit == 0) {
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/*
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* set master drive
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* address setup control register
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* is 32 bit !!!
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*/
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pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
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addrCtrl &= (~0xF);
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addrCtrl |= (unsigned int)pclk.address_time;
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pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
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/* now let's set the remaining registers */
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pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
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pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
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pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
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addrCtrl &= 0xF;
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} else {
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/*
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* set slave drive
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* address setup control register
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* is 32 bit !!!
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*/
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pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
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addrCtrl &= (~0xF0);
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addrCtrl |= ((unsigned int)pclk.address_time<<4);
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pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
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/* now let's set the remaining registers */
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pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
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pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
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pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
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addrCtrl >>= 4;
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addrCtrl &= 0xF;
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}
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
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"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
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drive->name, hwif->channel, drive->select.b.unit,
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addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
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#endif /* CY82C693_DEBUG_INFO */
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}
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/*
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* this function is called during init and is used to setup the cy82c693 chip
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*/
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static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
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{
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if (PCI_FUNC(dev->devfn) != 1)
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return 0;
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#ifdef CY82C693_SETDMA_CLOCK
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u8 data = 0;
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#endif /* CY82C693_SETDMA_CLOCK */
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/* write info about this verion of the driver */
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printk(KERN_INFO CY82_VERSION "\n");
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#ifdef CY82C693_SETDMA_CLOCK
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/* okay let's set the DMA clock speed */
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outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
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data = inb(CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
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name, data);
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#endif /* CY82C693_DEBUG_INFO */
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/*
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* for some reason sometimes the DMA controller
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* speed is set to ATCLK/2 ???? - we fix this here
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*
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* note: i don't know what causes this strange behaviour,
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* but even changing the dma speed doesn't solve it :-(
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* the ide performance is still only half the normal speed
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*
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* if anybody knows what goes wrong with my machine, please
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* let me know - ASK
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*/
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data |= 0x03;
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outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
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outb(data, CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
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name, data);
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#endif /* CY82C693_DEBUG_INFO */
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#endif /* CY82C693_SETDMA_CLOCK */
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return 0;
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}
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/*
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* the init function - called for each ide channel once
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*/
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static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
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{
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hwif->set_pio_mode = &cy82c693_set_pio_mode;
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hwif->set_dma_mode = &cy82c693_set_dma_mode;
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}
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static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
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{
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static ide_hwif_t *primary;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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if (PCI_FUNC(dev->devfn) == 1)
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primary = hwif;
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else {
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hwif->mate = primary;
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hwif->channel = 1;
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}
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}
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static const struct ide_port_info cy82c693_chipset __devinitdata = {
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.name = "CY82C693",
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.init_chipset = init_chipset_cy82c693,
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.init_iops = init_iops_cy82c693,
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.init_hwif = init_hwif_cy82c693,
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.chipset = ide_cy82c693,
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.host_flags = IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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.swdma_mask = ATA_SWDMA2,
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.mwdma_mask = ATA_MWDMA2,
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};
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static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct pci_dev *dev2;
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int ret = -ENODEV;
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/* CY82C693 is more than only a IDE controller.
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Function 1 is primary IDE channel, function 2 - secondary. */
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if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
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PCI_FUNC(dev->devfn) == 1) {
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dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
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ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
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/* We leak pci refs here but thats ok - we can't be unloaded */
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}
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return ret;
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}
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static const struct pci_device_id cy82c693_pci_tbl[] = {
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{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
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static struct pci_driver driver = {
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.name = "Cypress_IDE",
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.id_table = cy82c693_pci_tbl,
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.probe = cy82c693_init_one,
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};
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static int __init cy82c693_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(cy82c693_ide_init);
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MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
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MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
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MODULE_LICENSE("GPL");
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