173943b3da
The PCH implements a number of High Speed I/O (HSIO) lanes that are split between PCIe*, USB 3.0, SATA, GbE, USB OTG and SSIC. This patch shows the current power gating status of the available ModPhy Core lanes. This is done by sending a message to the PMC (MTPMC) that contains the XRAM register offset for the MPHY_CORE_STS_0 and MPHY_CORE_STS_1 and then by reading the response sent by the PMC (MFPMC). While enabling low power modes we often encounter situations when the ModPhy lanes are not power gated and it becomes hard to debug which lane is active and which is not in the absence of an external hardware debugger (JTAG/ITP). This patch eliminates the dependency on an external hardware debugger for reading the ModPhy Lanes power gating status. This patch requires PMC_READ_DISABLE setting to be disabled in the platform bios. cat /sys/kernel/debug/pmc_core/mphy_lanes_power_gating_status Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
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