16e604a437
A HW mapped level sensitive interrupt asserted by a device will not be put into the ap_list if it is disabled at the VGIC level. When it is enabled again, it will be inserted into the ap_list and written to a list register on guest entry regardless of the state of the device. We could argue that this can also happen on real hardware, when the command to enable the interrupt reached the GIC before the device had the chance to de-assert the interrupt signal; however, we emulate the distributor and redistributors in software and we can do better than that. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> |
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| .. | ||
| hyp | ||
| vgic | ||
| aarch32.c | ||
| arch_timer.c | ||
| arm.c | ||
| mmio.c | ||
| mmu.c | ||
| perf.c | ||
| pmu.c | ||
| psci.c | ||
| trace.h | ||