linux/drivers/gpu
Paulo Zanoni 1403c0d4d4 drm/i915: merge HSW and SNB PM irq handlers
Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does
and also processes the 2 additional VEBOX bits. So merge those
functions and wrap the VEBOX bits on a HAS_VEBOX check. This
check isn't really necessary since the bits are reserved on
SNB/IVB/VLV, but it's a good documentation on who uses them.

v2: - Change IS_HASWELL check to HAS_VEBOX

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-08-23 14:52:30 +02:00
..
drm drm/i915: merge HSW and SNB PM irq handlers 2013-08-23 14:52:30 +02:00
host1x gpu: host1x: Rework CPU syncpoint increment 2013-06-22 12:43:55 +02:00
vga
Makefile