1e939ea1bf
[Why&How] Several transitions were fixed that will allow Dynamic ODM and MPO transitions to be supported on DCN32. 1) Due to resource limitations, in certain scenarios that require an MPO plane to be split, the features cannot be combined with the current policy. This is due to unsafe transitions being required (OPP instance per MPCC being switched on active pipe is not supported by DCN), to support the split plane with ODM active as it moves across the viewport. Dynamic ODM will now be disabled when MPO is required. 2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for the next ODM pipe, which under previous power gating policy would result in programming a gated DSC HW block. New policy dynamically gates/un-gates DSC blocks when Dynamic ODM is active to support transitions on DCN32 only. 3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal transition so that all pipes which require their MPCC OPP instance to be changed have a full frame to be disabled before reprogramming. To solve this, the Dynamic ODM policy now utilizes minimal state transitions when entering or exiting 3 plane scenarios. 4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic ODM and MPO transitions. In summary, this commit fixes various transitions to support ODM->MPO and MPO->ODM. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HWSS_DCN32_H__
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#define __DC_HWSS_DCN32_H__
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#include "hw_sequencer_private.h"
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struct dc;
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void dcn32_dsc_pg_control(
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struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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void dcn32_enable_power_gating_plane(
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struct dce_hwseq *hws,
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bool enable);
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void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
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bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
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void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
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void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
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bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_input_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_output_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_stream_state *stream);
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void dcn32_init_hw(struct dc *dc);
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void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
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void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
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void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
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void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
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void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
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void dcn32_subvp_pipe_control_lock(struct dc *dc,
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struct dc_state *context,
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bool lock,
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bool should_lock_all_pipes,
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struct pipe_ctx *top_pipe_to_program,
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bool subvp_prev_use);
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void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
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struct dc_link_settings *link_settings);
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bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
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void dcn32_disable_link_output(struct dc_link *link,
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const struct link_resource *link_res,
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enum signal_type signal);
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void dcn32_update_phantom_vp_position(struct dc *dc,
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struct dc_state *context,
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struct pipe_ctx *phantom_pipe);
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bool dcn32_dsc_pg_status(
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struct dce_hwseq *hws,
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unsigned int dsc_inst);
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void dcn32_update_dsc_pg(struct dc *dc,
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struct dc_state *context,
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bool safe_to_disable);
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#endif /* __DC_HWSS_DCN32_H__ */
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