8eb060e101
Implement support for the ZiHintPause extension. The PAUSE instruction is a HINT that indicates the current hart’s rate of instruction retirement should be temporarily reduced or paused. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dao Lu <daolu@rivosinc.com> [Palmer: Some minor merge conflicts.] Link: https://lore.kernel.org/all/20220620201530.3929352-1-daolu@rivosinc.com/ Link: https://lore.kernel.org/all/20220811053356.17375-1-palmer@rivosinc.com/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
37 lines
830 B
C
37 lines
830 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_VDSO_PROCESSOR_H
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#define __ASM_VDSO_PROCESSOR_H
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#ifndef __ASSEMBLY__
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#include <linux/jump_label.h>
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#include <asm/barrier.h>
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#include <asm/hwcap.h>
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static inline void cpu_relax(void)
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{
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if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
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#ifdef __riscv_muldiv
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int dummy;
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/* In lieu of a halt instruction, induce a long-latency stall. */
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__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
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#endif
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} else {
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/*
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* Reduce instruction retirement.
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* This assumes the PC changes.
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*/
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#ifdef __riscv_zihintpause
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__asm__ __volatile__ ("pause");
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#else
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/* Encoding of the pause instruction */
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__asm__ __volatile__ (".4byte 0x100000F");
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#endif
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}
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barrier();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_VDSO_PROCESSOR_H */
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