b61a40afca
Current cache probe and flush methods have some drawbacks: 1, Assume there are 3 cache levels and only 3 levels; 2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive. However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are all valid. So, refactor the cache probe and flush methods to adapt more types of cache hierarchy. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
24 lines
634 B
C
24 lines
634 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _LOONGARCH_SETUP_H
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#define _LOONGARCH_SETUP_H
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#include <linux/types.h>
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#include <uapi/asm/setup.h>
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#define VECSIZE 0x200
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extern unsigned long eentry;
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extern unsigned long tlbrentry;
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extern void tlb_init(int cpu);
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extern void cpu_cache_init(void);
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extern void cache_error_setup(void);
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extern void per_cpu_trap_init(int cpu);
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extern void set_handler(unsigned long offset, void *addr, unsigned long len);
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extern void set_merr_handler(unsigned long offset, void *addr, unsigned long len);
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#endif /* __SETUP_H */
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