forked from Minki/linux
e1ced09797
Some initialization errors are reported with the existing OCTEON EDAC support patch. Also some parts have more than one memory controller. Fix the errors and add multiple controllers if present. Signed-off-by: David Daney <david.daney@cavium.com>
144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 Cavium, Inc.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#include <asm/octeon/cvmx.h>
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#include <asm/mipsregs.h>
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extern int register_co_cache_error_notifier(struct notifier_block *nb);
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extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
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extern unsigned long long cache_err_dcache[NR_CPUS];
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struct co_cache_error {
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struct notifier_block notifier;
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struct edac_device_ctl_info *ed;
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};
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/**
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* EDAC CPU cache error callback
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*
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* @event: non-zero if unrecoverable.
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*/
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static int co_cache_error_event(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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struct co_cache_error *p = container_of(this, struct co_cache_error,
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notifier);
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unsigned int core = cvmx_get_core_num();
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unsigned int cpu = smp_processor_id();
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u64 icache_err = read_octeon_c0_icacheerr();
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u64 dcache_err;
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if (event) {
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dcache_err = cache_err_dcache[core];
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cache_err_dcache[core] = 0;
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} else {
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dcache_err = read_octeon_c0_dcacheerr();
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}
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if (icache_err & 1) {
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edac_device_printk(p->ed, KERN_ERR,
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"CacheErr (Icache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
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(unsigned long long)icache_err, core, cpu,
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read_c0_errorepc());
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write_octeon_c0_icacheerr(0);
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edac_device_handle_ce(p->ed, cpu, 1, "icache");
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}
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if (dcache_err & 1) {
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edac_device_printk(p->ed, KERN_ERR,
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"CacheErr (Dcache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
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(unsigned long long)dcache_err, core, cpu,
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read_c0_errorepc());
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if (event)
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edac_device_handle_ue(p->ed, cpu, 0, "dcache");
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else
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edac_device_handle_ce(p->ed, cpu, 0, "dcache");
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/* Clear the error indication */
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if (OCTEON_IS_MODEL(OCTEON_FAM_2))
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write_octeon_c0_dcacheerr(1);
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else
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write_octeon_c0_dcacheerr(0);
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}
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return NOTIFY_STOP;
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}
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static int __devinit co_cache_error_probe(struct platform_device *pdev)
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{
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struct co_cache_error *p = devm_kzalloc(&pdev->dev, sizeof(*p),
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GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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p->notifier.notifier_call = co_cache_error_event;
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platform_set_drvdata(pdev, p);
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p->ed = edac_device_alloc_ctl_info(0, "cpu", num_possible_cpus(),
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"cache", 2, 0, NULL, 0,
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edac_device_alloc_index());
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if (!p->ed)
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goto err;
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p->ed->dev = &pdev->dev;
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p->ed->dev_name = dev_name(&pdev->dev);
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p->ed->mod_name = "octeon-cpu";
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p->ed->ctl_name = "cache";
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if (edac_device_add_device(p->ed)) {
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pr_err("%s: edac_device_add_device() failed\n", __func__);
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goto err1;
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}
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register_co_cache_error_notifier(&p->notifier);
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return 0;
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err1:
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edac_device_free_ctl_info(p->ed);
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err:
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return -ENXIO;
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}
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static int co_cache_error_remove(struct platform_device *pdev)
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{
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struct co_cache_error *p = platform_get_drvdata(pdev);
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unregister_co_cache_error_notifier(&p->notifier);
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edac_device_del_device(&pdev->dev);
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edac_device_free_ctl_info(p->ed);
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return 0;
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}
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static struct platform_driver co_cache_error_driver = {
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.probe = co_cache_error_probe,
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.remove = co_cache_error_remove,
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.driver = {
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.name = "octeon_pc_edac",
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}
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};
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module_platform_driver(co_cache_error_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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