b3d6aba8bd
This allows us to introduce timers in DT in next commit The core clk frequency hack in AXS103 platform is also extended, where the core clk feeding into timers is updated in-place in FDT. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
/*
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* Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
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*/
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/include/ "skeleton_hs.dtsi"
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/ {
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compatible = "snps,arc";
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clock-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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core_intc: archs-intc@cpu {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <2403200>;
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interrupt-parent = <&core_intc>;
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interrupts = <19>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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};
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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interrupts = < 18 >;
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};
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x40000000>;
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MiB */
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};
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};
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