forked from Minki/linux
74ded659a7
This patch adds USBOTG devicetree node of Phytec PCM038 module. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
318 lines
6.7 KiB
Plaintext
318 lines
6.7 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx27.dtsi"
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/ {
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model = "Phytec pcm038";
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compatible = "phytec,imx27-pcm038", "fsl,imx27";
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memory {
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reg = <0xa0000000 0x08000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_5v0: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "5V0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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};
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&audmux {
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status = "okay";
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/* SSI0 <=> PINS_4 (MC13783 Audio) */
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ssi0 {
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fsl,audmux-port = <0>;
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fsl,port-config = <0xcb205000>;
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};
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pins4 {
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fsl,audmux-port = <2>;
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fsl,port-config = <0x00001000>;
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};
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};
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&cspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cspi1>;
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic: mc13783@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mc13783";
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reg = <0>;
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spi-cs-high;
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spi-max-frequency = <20000000>;
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interrupt-parent = <&gpio2>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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fsl,mc13xxx-uses-adc;
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fsl,mc13xxx-uses-rtc;
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pmicleds: leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
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};
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regulators {
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/* SW1A and SW1B joined operation */
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sw1_reg: sw1a {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1520000>;
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regulator-always-on;
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regulator-boot-on;
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};
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/* SW2A and SW2B joined operation */
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sw2_reg: sw2a {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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sw3_reg: sw3 {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vaudio_reg: vaudio {
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regulator-always-on;
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regulator-boot-on;
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};
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violo_reg: violo {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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viohi_reg: viohi {
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regulator-always-on;
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regulator-boot-on;
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};
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vgen_reg: vgen {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vcam_reg: vcam {
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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vrf1_reg: vrf1 {
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regulator-min-microvolt = <2775000>;
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regulator-max-microvolt = <2775000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vrf2_reg: vrf2 {
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regulator-min-microvolt = <2775000>;
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regulator-max-microvolt = <2775000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vmmc1_reg: vmmc1 {
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3000000>;
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};
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gpo1_reg: gpo1 { };
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pwgt1spi_reg: pwgt1spi {
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regulator-always-on;
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};
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};
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};
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};
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&fec {
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phy-mode = "mii";
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phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
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phy-supply = <®_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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at24@52 {
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compatible = "at,24c32";
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pagesize = <32>;
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reg = <0x52>;
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};
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pcf8563@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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lm75@4a {
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compatible = "national,lm75";
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reg = <0x4a>;
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};
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};
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&iomuxc {
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imx27_phycore_som {
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pinctrl_cspi1: cspi1grp {
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fsl,pins = <
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MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
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MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
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MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
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MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
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MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX27_PAD_SD3_CMD__FEC_TXD0 0x0
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MX27_PAD_SD3_CLK__FEC_TXD1 0x0
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MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
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MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
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MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
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MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
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MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
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MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
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MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
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MX27_PAD_ATA_DATA7__FEC_MDC 0x0
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MX27_PAD_ATA_DATA8__FEC_CRS 0x0
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MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
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MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
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MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
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MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
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MX27_PAD_ATA_DATA13__FEC_COL 0x0
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MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
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MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
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MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
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MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
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>;
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};
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pinctrl_nfc: nfcgrp {
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fsl,pins = <
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MX27_PAD_NFRB__NFRB 0x0
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MX27_PAD_NFCLE__NFCLE 0x0
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MX27_PAD_NFWP_B__NFWP_B 0x0
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MX27_PAD_NFCE_B__NFCE_B 0x0
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MX27_PAD_NFALE__NFALE 0x0
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MX27_PAD_NFRE_B__NFRE_B 0x0
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MX27_PAD_NFWE_B__NFWE_B 0x0
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>;
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};
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pinctrl_usbotg: usbotggrp {
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fsl,pins = <
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MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
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MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
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MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
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MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
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MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
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MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
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MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
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MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
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MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
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MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
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MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
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MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
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>;
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};
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};
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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&usbotg {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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dr_mode = "otg";
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phy_type = "ulpi";
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vbus-supply = <&sw3_reg>;
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status = "okay";
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};
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&usbphy0 {
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vcc-supply = <&sw3_reg>;
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};
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&weim {
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status = "okay";
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nor: nor@c0000000 {
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compatible = "cfi-flash";
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reg = <0 0x00000000 0x02000000>;
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bank-width = <2>;
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linux,mtd-name = "physmap-flash.0";
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fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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sram: sram@c8000000 {
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compatible = "mtd-ram";
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reg = <1 0x00000000 0x00800000>;
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bank-width = <2>;
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linux,mtd-name = "mtd-ram.0";
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fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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