forked from Minki/linux
96579a4e56
Transfer state machine in this driver does not need to set/unset pointer to chip data between queueing and finalizing message as it is not actually used as a state info itself but just pointer passing. Since this per SPI device specific chip data is already carried in ctldata use that and remove pointer to chip data from driver data. While at it, group initialized variables before uninitialized variables in pump_transfers(). Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
250 lines
6.2 KiB
C
250 lines
6.2 KiB
C
/*
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* PXA2xx SPI DMA engine support.
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*
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* Copyright (C) 2013, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/scatterlist.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include "spi-pxa2xx.h"
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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bool error)
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{
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struct spi_message *msg = drv_data->master->cur_msg;
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/*
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* It is possible that one CPU is handling ROR interrupt and other
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* just gets DMA completion. Calling pump_transfers() twice for the
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* same transfer leads to problems thus we prevent concurrent calls
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* by using ->dma_running.
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*/
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if (atomic_dec_and_test(&drv_data->dma_running)) {
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/*
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* If the other CPU is still handling the ROR interrupt we
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* might not know about the error yet. So we re-check the
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* ROR bit here before we clear the status register.
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*/
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if (!error) {
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u32 status = pxa2xx_spi_read(drv_data, SSSR)
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& drv_data->mask_sr;
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error = status & SSSR_ROR;
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}
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/* Clear status & disable interrupts */
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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if (!pxa25x_ssp_comp(drv_data))
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pxa2xx_spi_write(drv_data, SSTO, 0);
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if (!error) {
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msg->actual_length += drv_data->len;
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msg->state = pxa2xx_spi_next_transfer(drv_data);
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} else {
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/* In case we got an error we disable the SSP now */
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pxa2xx_spi_write(drv_data, SSCR0,
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pxa2xx_spi_read(drv_data, SSCR0)
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& ~SSCR0_SSE);
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msg->state = ERROR_STATE;
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}
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tasklet_schedule(&drv_data->pump_transfers);
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}
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}
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static void pxa2xx_spi_dma_callback(void *data)
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{
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pxa2xx_spi_dma_transfer_complete(data, false);
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}
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static struct dma_async_tx_descriptor *
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pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
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enum dma_transfer_direction dir)
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{
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struct chip_data *chip =
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spi_get_ctldata(drv_data->master->cur_msg->spi);
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struct spi_transfer *xfer = drv_data->cur_transfer;
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enum dma_slave_buswidth width;
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struct dma_slave_config cfg;
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struct dma_chan *chan;
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struct sg_table *sgt;
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int ret;
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switch (drv_data->n_bytes) {
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case 1:
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width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case 2:
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width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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default:
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width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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}
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memset(&cfg, 0, sizeof(cfg));
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cfg.direction = dir;
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if (dir == DMA_MEM_TO_DEV) {
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cfg.dst_addr = drv_data->ssdr_physical;
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cfg.dst_addr_width = width;
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cfg.dst_maxburst = chip->dma_burst_size;
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sgt = &xfer->tx_sg;
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chan = drv_data->master->dma_tx;
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} else {
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cfg.src_addr = drv_data->ssdr_physical;
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cfg.src_addr_width = width;
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cfg.src_maxburst = chip->dma_burst_size;
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sgt = &xfer->rx_sg;
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chan = drv_data->master->dma_rx;
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}
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ret = dmaengine_slave_config(chan, &cfg);
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if (ret) {
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dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
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return NULL;
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}
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return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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}
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irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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u32 status;
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status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
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if (status & SSSR_ROR) {
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dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
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dmaengine_terminate_async(drv_data->master->dma_rx);
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dmaengine_terminate_async(drv_data->master->dma_tx);
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pxa2xx_spi_dma_transfer_complete(drv_data, true);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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{
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struct dma_async_tx_descriptor *tx_desc, *rx_desc;
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int err;
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tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
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if (!tx_desc) {
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dev_err(&drv_data->pdev->dev,
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"failed to get DMA TX descriptor\n");
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err = -EBUSY;
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goto err_tx;
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}
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rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
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if (!rx_desc) {
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dev_err(&drv_data->pdev->dev,
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"failed to get DMA RX descriptor\n");
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err = -EBUSY;
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goto err_rx;
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}
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/* We are ready when RX completes */
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rx_desc->callback = pxa2xx_spi_dma_callback;
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rx_desc->callback_param = drv_data;
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dmaengine_submit(rx_desc);
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dmaengine_submit(tx_desc);
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return 0;
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err_rx:
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dmaengine_terminate_async(drv_data->master->dma_tx);
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err_tx:
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return err;
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}
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void pxa2xx_spi_dma_start(struct driver_data *drv_data)
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{
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dma_async_issue_pending(drv_data->master->dma_rx);
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dma_async_issue_pending(drv_data->master->dma_tx);
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atomic_set(&drv_data->dma_running, 1);
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}
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int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
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{
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struct pxa2xx_spi_master *pdata = drv_data->master_info;
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struct device *dev = &drv_data->pdev->dev;
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struct spi_master *master = drv_data->master;
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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master->dma_tx = dma_request_slave_channel_compat(mask,
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pdata->dma_filter, pdata->tx_param, dev, "tx");
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if (!master->dma_tx)
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return -ENODEV;
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master->dma_rx = dma_request_slave_channel_compat(mask,
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pdata->dma_filter, pdata->rx_param, dev, "rx");
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if (!master->dma_rx) {
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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return -ENODEV;
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}
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return 0;
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}
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void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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{
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struct spi_master *master = drv_data->master;
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if (master->dma_rx) {
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dmaengine_terminate_sync(master->dma_rx);
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dma_release_channel(master->dma_rx);
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master->dma_rx = NULL;
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}
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if (master->dma_tx) {
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dmaengine_terminate_sync(master->dma_tx);
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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}
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}
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int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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struct spi_device *spi,
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u8 bits_per_word, u32 *burst_code,
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u32 *threshold)
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{
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struct pxa2xx_spi_chip *chip_info = spi->controller_data;
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/*
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* If the DMA burst size is given in chip_info we use that,
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* otherwise we use the default. Also we use the default FIFO
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* thresholds for now.
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*/
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*burst_code = chip_info ? chip_info->dma_burst_size : 1;
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*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
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| SSCR1_TxTresh(TX_THRESH_DFLT);
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return 0;
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}
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