0da6587041
This patch replaces all custom samsung,power-domain dt properties with generic power domain bindings and updates documentation Samsung's devices referring to old binding. Suggested-by: Kevin Hilman <khilman@kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> [javier.martinez@collabora.co.uk: tested on the Exynos5800 Peach Pi Chromebook] Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
48 lines
1.6 KiB
Plaintext
48 lines
1.6 KiB
Plaintext
* Samsung Exynos Power Domains
|
|
|
|
Exynos processors include support for multiple power domains which are used
|
|
to gate power to one or more peripherals on the processor.
|
|
|
|
Required Properties:
|
|
- compatible: should be one of the following.
|
|
* samsung,exynos4210-pd - for exynos4210 type power domain.
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
- #power-domain-cells: number of cells in power domain specifier;
|
|
must be 0.
|
|
|
|
Optional Properties:
|
|
- clocks: List of clock handles. The parent clocks of the input clocks to the
|
|
devices in this power domain are set to oscclk before power gating
|
|
and restored back after powering on a domain. This is required for
|
|
all domains which are powered on and off and not required for unused
|
|
domains.
|
|
- clock-names: The following clocks can be specified:
|
|
- oscclk: Oscillator clock.
|
|
- pclkN, clkN: Pairs of parent of input clock and input clock to the
|
|
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
|
|
are supported currently.
|
|
|
|
Node of a device using power domains must have a power-domains property
|
|
defined with a phandle to respective power domain.
|
|
|
|
Example:
|
|
|
|
lcd0: power-domain-lcd0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10023C00 0x10>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
mfc_pd: power-domain@10044060 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10044060 0x20>;
|
|
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
|
|
<&clock CLK_MOUT_USER_ACLK333>;
|
|
clock-names = "oscclk", "pclk0", "clk0";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
See Documentation/devicetree/bindings/power/power_domain.txt for description
|
|
of consumer-side bindings.
|