Talha Nassar 0b904c890a drm/i915/icl: restore WaEnableFloatBlendOptimization ... Enables blend optimization for floating point RTs This restores the workaround that was reverted in c358514ba8 ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization""). The revert was due to the register write seemingly not sticking, but the HW team has confirmed that this is because the register is WO and that the workaround is indeed required. Here the wa is added with a mask of 0 since the register is WO. References: https://hsdes.intel.com/resource/1408134172 References: https://bugs.freedesktop.org/show_bug.cgi?id=107338 Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Talha Nassar <talha.nassar@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/1548983324-15344-4-git-send-email-talha.nassar@intel.com		2019-02-01 08:39:53 +00:00
..
drm	drm/i915/icl: restore WaEnableFloatBlendOptimization	2019-02-01 08:39:53 +00:00
host1x	gpu: host1x: Add Tegra194 support	2018-11-29 17:11:49 +01:00
ipu-v3	gpu: ipu-v3: image-convert: allow three rows or columns	2018-11-05 14:40:08 +01:00
vga	drm-misc-next for v4.21, part 1:	2018-11-19 10:40:33 +10:00
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