If the HW implements round-robin interrupt delivery, this enables multiple cpu's (which are part of the user specified interrupt smp_affinity mask and belong to the same x2apic cluster) to service the interrupt. Also if the platform supports Power Aware Interrupt Routing, then this enables the interrupt to be routed to an idle cpu or a busy cpu depending on the perf/power bias tunable. We are now grouping all the cpu's in a cluster to one vector domain. So that will limit the total number of interrupt sources handled by Linux. Previously we support "cpu-count * available-vectors-per-cpu" interrupt sources but this will now reduce to "cpu-count/16 * available-vectors-per-cpu". Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: gorcunov@openvz.org Cc: agordeev@redhat.com Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1337644682-19854-2-git-send-email-suresh.b.siddha@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
192 lines
4.7 KiB
C
192 lines
4.7 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/dmar.h>
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#include <asm/smp.h>
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#include <asm/x2apic.h>
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int x2apic_phys;
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static struct apic apic_x2apic_phys;
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static int set_x2apic_phys_mode(char *arg)
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{
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x2apic_phys = 1;
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return 0;
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}
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early_param("x2apic_phys", set_x2apic_phys_mode);
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (x2apic_phys)
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return x2apic_enabled();
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else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
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(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
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x2apic_enabled()) {
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printk(KERN_DEBUG "System requires x2apic physical mode\n");
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return 1;
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}
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else
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return 0;
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}
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static void
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__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
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{
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unsigned long query_cpu;
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unsigned long this_cpu;
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unsigned long flags;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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this_cpu = smp_processor_id();
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for_each_cpu(query_cpu, mask) {
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if (apic_dest == APIC_DEST_ALLBUT && this_cpu == query_cpu)
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continue;
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__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
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vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
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}
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static void
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x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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int cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int
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x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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return per_cpu(x86_cpu_to_apicid, cpu);
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}
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static void init_x2apic_ldr(void)
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{
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}
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static int x2apic_phys_probe(void)
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{
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if (x2apic_mode && x2apic_phys)
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return 1;
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return apic == &apic_x2apic_phys;
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}
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/*
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* Each logical cpu is in its own vector allocation domain.
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*/
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static struct apic apic_x2apic_phys = {
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.name = "physical x2apic",
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.probe = x2apic_phys_probe,
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.apic_id_valid = x2apic_apic_id_valid,
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.apic_id_registered = x2apic_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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.irq_dest_mode = 0, /* physical */
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.target_cpus = x2apic_target_cpus,
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.disable_esr = 0,
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.dest_logical = 0,
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.check_apicid_used = NULL,
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.check_apicid_present = NULL,
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.vector_allocation_domain = x2apic_vector_allocation_domain,
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.init_apic_ldr = init_x2apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.multi_timer_check = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = x2apic_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_get_apic_id,
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.set_apic_id = x2apic_set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_self = x2apic_send_IPI_self,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = NULL,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = NULL,
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.read = native_apic_msr_read,
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.write = native_apic_msr_write,
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.eoi_write = native_apic_msr_eoi_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.wait_icr_idle = native_x2apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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apic_driver(apic_x2apic_phys);
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