forked from Minki/linux
1191ccb34c
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to sparc, in the
same vein as the dummy definitions for the relaxed read accessors. The
existing relaxed read{b,w,l} accessors are moved into asm/io.h, since
they are identical between 32-bit and 64-bit machines.
Acked-by: "David S. Miller" <davem@davemloft.net>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
169 lines
3.7 KiB
C
169 lines
3.7 KiB
C
#ifndef __SPARC_IO_H
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#define __SPARC_IO_H
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#include <linux/kernel.h>
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#include <linux/ioport.h> /* struct resource */
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#define IO_SPACE_LIMIT 0xffffffff
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#define memset_io(d,c,sz) _memset_io(d,c,sz)
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#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
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#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
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#include <asm-generic/io.h>
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static inline void _memset_io(volatile void __iomem *dst,
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int c, __kernel_size_t n)
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{
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volatile void __iomem *d = dst;
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while (n--) {
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writeb(c, d);
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d++;
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}
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}
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static inline void _memcpy_fromio(void *dst, const volatile void __iomem *src,
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__kernel_size_t n)
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{
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char *d = dst;
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while (n--) {
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char tmp = readb(src);
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*d++ = tmp;
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src++;
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}
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}
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static inline void _memcpy_toio(volatile void __iomem *dst, const void *src,
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__kernel_size_t n)
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{
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const char *s = src;
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volatile void __iomem *d = dst;
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while (n--) {
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char tmp = *s++;
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writeb(tmp, d);
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d++;
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}
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}
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/*
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* SBus accessors.
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*
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* SBus has only one, memory mapped, I/O space.
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* We do not need to flip bytes for SBus of course.
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*/
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static inline u8 sbus_readb(const volatile void __iomem *addr)
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{
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return *(__force volatile u8 *)addr;
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}
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static inline u16 sbus_readw(const volatile void __iomem *addr)
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{
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return *(__force volatile u16 *)addr;
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}
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static inline u32 sbus_readl(const volatile void __iomem *addr)
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{
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return *(__force volatile u32 *)addr;
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}
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static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
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{
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*(__force volatile u8 *)addr = b;
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}
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static inline void sbus_writew(u16 w, volatile void __iomem *addr)
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{
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*(__force volatile u16 *)addr = w;
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}
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static inline void sbus_writel(u32 l, volatile void __iomem *addr)
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{
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*(__force volatile u32 *)addr = l;
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}
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static inline void sbus_memset_io(volatile void __iomem *__dst, int c,
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__kernel_size_t n)
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{
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while(n--) {
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sbus_writeb(c, __dst);
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__dst++;
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}
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}
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static inline void sbus_memcpy_fromio(void *dst,
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const volatile void __iomem *src,
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__kernel_size_t n)
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{
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char *d = dst;
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while (n--) {
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char tmp = sbus_readb(src);
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*d++ = tmp;
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src++;
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}
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}
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static inline void sbus_memcpy_toio(volatile void __iomem *dst,
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const void *src,
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__kernel_size_t n)
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{
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const char *s = src;
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volatile void __iomem *d = dst;
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while (n--) {
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char tmp = *s++;
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sbus_writeb(tmp, d);
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d++;
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}
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}
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#ifdef __KERNEL__
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/*
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* Bus number may be embedded in the higher bits of the physical address.
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* This is why we have no bus number argument to ioremap().
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*/
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void __iomem *ioremap(unsigned long offset, unsigned long size);
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#define ioremap_nocache(X,Y) ioremap((X),(Y))
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#define ioremap_wc(X,Y) ioremap((X),(Y))
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void iounmap(volatile void __iomem *addr);
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/* Create a virtual mapping cookie for an IO port range */
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void __iomem *ioport_map(unsigned long port, unsigned int nr);
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void ioport_unmap(void __iomem *);
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/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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struct pci_dev;
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void pci_iounmap(struct pci_dev *dev, void __iomem *);
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/*
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* At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
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* so rtc_port is static in it. This should not change unless a new
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* hardware pops up.
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*/
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#define RTC_PORT(x) (rtc_port + (x))
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#define RTC_ALWAYS_BCD 0
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static inline int sbus_can_dma_64bit(void)
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{
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return 0; /* actually, sparc_cpu_model==sun4d */
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}
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static inline int sbus_can_burst64(void)
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{
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return 0; /* actually, sparc_cpu_model==sun4d */
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}
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struct device;
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void sbus_set_sbus64(struct device *, int);
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#endif
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#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
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#endif /* !(__SPARC_IO_H) */
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