0a30284b9f
Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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| .. | ||
| clk-div6.c | ||
| clk-div6.h | ||
| clk-emev2.c | ||
| clk-mstp.c | ||
| clk-r8a73a4.c | ||
| clk-r8a7740.c | ||
| clk-r8a7778.c | ||
| clk-r8a7779.c | ||
| clk-rcar-gen2.c | ||
| clk-rz.c | ||
| clk-sh73a0.c | ||
| Kconfig | ||
| Makefile | ||
| r8a7795-cpg-mssr.c | ||
| r8a7796-cpg-mssr.c | ||
| rcar-gen3-cpg.c | ||
| rcar-gen3-cpg.h | ||
| renesas-cpg-mssr.c | ||
| renesas-cpg-mssr.h | ||