linux/drivers/gpu/drm/amd/display/dc/inc
Krunoslav Kovac 0975780913 drm/amd/display: Set gamma not working on MPO planes
[Why]
Set gamma not working on certain planes in MPO configuration
Root cause is that video format (YUV-420) isn't allowed for IGAM where
gamma is applied.
Fix is not easy though:
1. allowing will not work because IGAM is before ICSC so RGB gamma would
be applied on YUV pixels.
2. Moving OS gamma to DGAM or RGAM resulted in weird artifacts.

Ultimately the root cause for these artifacts was due to handling end
points and the fact that YUV->RGB conversion will frequently "overshoot"
FP 1.0 value. DCE  has a single end point and slope, so we would take max.
In nightlight mode, blue channel is reduced, sometimes to flat 0 line,
but red is virtually unchanged. Any "overshot" in blue will be clipped
to 1 (max R,G,B) instead of max blue value.

[How]
Fortunately, this can be fixed on DCN where we have end point and slope
for all three color channels. We cannot fix this problem on DCE.

Other things fixed:
- switch (back) to using RGAM for OS gamma instead of IGAM
- add coeffs for 709 YUV->RGB (we used RGB->YUV for both conversions)
- switch color temperature method to scaled bradford - otherwise we would
have clipping problems that caused us to switch to IGAM for OS gamma
in the first place.
- comments and some minor improvements - there are some more issues but
they will be addressed in separate commits.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:31 -05:00
..
hw drm/amd/display: Set gamma not working on MPO planes 2018-11-05 14:21:31 -05:00
bw_fixed.h drm/amd/display: explicit uint64_t casting 2018-11-05 14:20:50 -05:00
clock_source.h drm/amd/display: remove unused clk_src code 2018-09-10 22:42:55 -05:00
compressor.h drm/amd/display: Initial prototype of FBC implementation 2017-09-26 18:15:56 -04:00
core_status.h drm/amd/display: Add timing validation against dongle cap 2017-11-28 17:54:16 -05:00
core_types.h drm/amd/display: add dccg block 2018-11-05 14:20:48 -05:00
custom_float.h drm/amd/display: Enable regamma 25 segments and use double buffer. 2017-09-26 17:14:18 -04:00
dc_link_ddc.h drm/amd/display: Return aux replies directly to DRM 2018-07-13 14:48:36 -05:00
dc_link_dp.h drm/amd/display: Retry link training again 2018-07-27 09:07:42 -05:00
dce_calcs.h drm/amdgpu/display: remove VEGAM config option 2018-05-18 16:08:18 -05:00
dcn_calcs.h drm/amd/display: rename dccg to clk_mgr 2018-11-05 14:20:48 -05:00
hw_sequencer.h drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead 2018-11-05 14:20:40 -05:00
link_hwss.h drm/amd/display: add eDP 1.2+ polling for T7 2018-02-19 14:19:34 -05:00
reg_helper.h drm/amd/display: generic indirect register access 2018-07-13 14:47:33 -05:00
resource.h drm/amd/display: move pplib/smu notification to dccg block 2018-11-05 14:20:40 -05:00