08f051eda3
The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush the instruction cache whenever marking a dirty page as executable in order to preserve the correct system behavior. Local instruction caches aren't that scary (our implementations actually flush the cache, but RISC-V is defined to allow higher-performance implementations to exist), but RISC-V defines no way to perform an instruction cache shootdown. When explicitly asked to do so we can shoot down remote instruction caches via an IPI, but this is a bit on the slow side. Instead of requiring an IPI to all harts whenever marking a page as executable, we simply flush the currently running harts. In order to maintain correct behavior, we additionally mark every other hart as needing a deferred instruction cache which will be taken before anything runs on it. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
67 lines
1.8 KiB
C
67 lines
1.8 KiB
C
/*
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* Copyright (C) 2009 Chen Liqin <liqin.chen@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ASM_RISCV_TLBFLUSH_H
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#define _ASM_RISCV_TLBFLUSH_H
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#ifdef CONFIG_MMU
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#include <linux/mm_types.h>
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/* Flush entire local TLB */
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static inline void local_flush_tlb_all(void)
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{
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__asm__ __volatile__ ("sfence.vma" : : : "memory");
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}
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/* Flush one page from local TLB */
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static inline void local_flush_tlb_page(unsigned long addr)
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{
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__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
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}
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#ifndef CONFIG_SMP
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#define flush_tlb_all() local_flush_tlb_all()
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#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
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#define flush_tlb_range(vma, start, end) local_flush_tlb_all()
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#else /* CONFIG_SMP */
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#include <asm/sbi.h>
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#define flush_tlb_all() sbi_remote_sfence_vma(0, 0, -1)
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#define flush_tlb_page(vma, addr) flush_tlb_range(vma, addr, 0)
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#define flush_tlb_range(vma, start, end) \
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sbi_remote_sfence_vma(0, start, (end) - (start))
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#endif /* CONFIG_SMP */
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/* Flush the TLB entries of the specified mm context */
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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flush_tlb_all();
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}
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/* Flush a range of kernel pages */
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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flush_tlb_all();
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}
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#endif /* CONFIG_MMU */
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#endif /* _ASM_RISCV_TLBFLUSH_H */
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