08f051eda3
The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush the instruction cache whenever marking a dirty page as executable in order to preserve the correct system behavior. Local instruction caches aren't that scary (our implementations actually flush the cache, but RISC-V is defined to allow higher-performance implementations to exist), but RISC-V defines no way to perform an instruction cache shootdown. When explicitly asked to do so we can shoot down remote instruction caches via an IPI, but this is a bit on the slow side. Instead of requiring an IPI to all harts whenever marking a page as executable, we simply flush the currently running harts. In order to maintain correct behavior, we additionally mark every other hart as needing a deferred instruction cache which will be taken before anything runs on it. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/*
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* Copyright (C) 2015 Regents of the University of California
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <asm-generic/cacheflush.h>
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#undef flush_icache_range
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#undef flush_icache_user_range
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#undef flush_dcache_page
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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#define PG_dcache_clean PG_arch_1
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static inline void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range(start, end) flush_icache_all()
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#define flush_icache_user_range(vma, pg, addr, len) flush_icache_all()
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#ifndef CONFIG_SMP
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#define flush_icache_all() local_flush_icache_all()
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#define flush_icache_mm(mm, local) flush_icache_all()
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#else /* CONFIG_SMP */
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#define flush_icache_all() sbi_remote_fence_i(0)
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void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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