forked from Minki/linux
96068e6b4d
The *_RELEASE macros don't tell me anything. In some cases the version in the macro contradicts the version in the comments. Anyway, the Linux kernel version is sufficient information. Remove these macros to improve readability. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.de> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* DTC controller, taken from T128 driver by...
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*/
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#ifndef DTC3280_H
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#define DTC3280_H
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#define DTCDEBUG 0
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#define DTCDEBUG_INIT 0x1
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#define DTCDEBUG_TRANSFER 0x2
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#ifndef CMD_PER_LUN
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#define CMD_PER_LUN 2
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#endif
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#ifndef CAN_QUEUE
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#define CAN_QUEUE 32
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#endif
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#define NCR5380_implementation_fields \
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void __iomem *base
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#define NCR5380_local_declare() \
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void __iomem *base
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#define NCR5380_setup(instance) \
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base = ((struct NCR5380_hostdata *)(instance)->hostdata)->base
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#define DTC_address(reg) (base + DTC_5380_OFFSET + reg)
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#define dbNCR5380_read(reg) \
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(rval=readb(DTC_address(reg)), \
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(((unsigned char) printk("DTC : read register %d at addr %p is: %02x\n"\
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, (reg), DTC_address(reg), rval)), rval ) )
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#define dbNCR5380_write(reg, value) do { \
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printk("DTC : write %02x to register %d at address %p\n", \
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(value), (reg), DTC_address(reg)); \
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writeb(value, DTC_address(reg));} while(0)
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#if !(DTCDEBUG & DTCDEBUG_TRANSFER)
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#define NCR5380_read(reg) (readb(DTC_address(reg)))
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#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
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#else
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#define NCR5380_read(reg) (readb(DTC_address(reg)))
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#define xNCR5380_read(reg) \
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(((unsigned char) printk("DTC : read register %d at address %p\n"\
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, (reg), DTC_address(reg))), readb(DTC_address(reg)))
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#define NCR5380_write(reg, value) do { \
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printk("DTC : write %02x to register %d at address %p\n", \
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(value), (reg), DTC_address(reg)); \
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writeb(value, DTC_address(reg));} while(0)
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#endif
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#define NCR5380_intr dtc_intr
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#define NCR5380_queue_command dtc_queue_command
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#define NCR5380_abort dtc_abort
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#define NCR5380_bus_reset dtc_bus_reset
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#define NCR5380_info dtc_info
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#define NCR5380_show_info dtc_show_info
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#define NCR5380_write_info dtc_write_info
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/* 15 12 11 10
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1001 1100 0000 0000 */
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#define DTC_IRQS 0x9c00
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#endif /* DTC3280_H */
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