0735cfdf0a
Mali DP500 operates in continuous writeback mode (writes frame content until stopped) and it needs special handling in order to behave like a one-shot writeback engine. The original state machine added for DP500 was a bit fragile, as it did not handle correctly cases where a new atomic commit was in progress when the SE IRQ happens and it would commit some partial updates. Improve the handling by adding a parameter to the set_config_valid() function to clear the config valid bit in hardware before starting a new commit and by introducing a MW_RESTART state in the writeback state machine to cater for the case where a new writeback commit gets submitted while the last one is still being active. Reported-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> |
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| .. | ||
| hdlcd_crtc.c | ||
| hdlcd_drv.c | ||
| hdlcd_drv.h | ||
| hdlcd_regs.h | ||
| Kconfig | ||
| Makefile | ||
| malidp_crtc.c | ||
| malidp_drv.c | ||
| malidp_drv.h | ||
| malidp_hw.c | ||
| malidp_hw.h | ||
| malidp_mw.c | ||
| malidp_mw.h | ||
| malidp_planes.c | ||
| malidp_regs.h | ||