b77e995e3b
Currently we don't have any coverage of the syscall ABI so let's add a very dumb test program which sets up register patterns, does a sysscall and then checks that the register state after the syscall matches what we expect. The program is written in an extremely simplistic fashion with the goal of making it easy to verify that it's doing what it thinks it's doing, it is not a model of how one should write actual code. Currently we validate the general purpose, FPSIMD and SVE registers. There are other thing things that could be covered like FPCR and flags registers, these can be covered incrementally - my main focus at the minute is covering the ABI for the SVE registers. The program repeats the tests for all possible SVE vector lengths in case some vector length specific optimisation causes issues, as well as testing FPSIMD only. It tries two syscalls, getpid() and sched_yield(), in an effort to cover both immediate return to userspace and scheduling another task though there are no guarantees which cases will be hit. A new test directory "abi" is added to hold the test, it doesn't seem to fit well into any of the existing directories. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211210184133.320748-7-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
241 lines
5.6 KiB
ArmAsm
241 lines
5.6 KiB
ArmAsm
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2021 ARM Limited.
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//
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// Assembly portion of the syscall ABI test
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//
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// Load values from memory into registers, invoke a syscall and save the
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// register values back to memory for later checking. The syscall to be
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// invoked is configured in x8 of the input GPR data.
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//
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// x0: SVE VL, 0 for FP only
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//
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// GPRs: gpr_in, gpr_out
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// FPRs: fpr_in, fpr_out
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// Zn: z_in, z_out
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// Pn: p_in, p_out
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// FFR: ffr_in, ffr_out
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.arch_extension sve
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.globl do_syscall
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do_syscall:
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// Store callee saved registers x19-x29 (80 bytes) plus x0 and x1
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stp x29, x30, [sp, #-112]!
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mov x29, sp
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stp x0, x1, [sp, #16]
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stp x19, x20, [sp, #32]
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stp x21, x22, [sp, #48]
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stp x23, x24, [sp, #64]
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stp x25, x26, [sp, #80]
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stp x27, x28, [sp, #96]
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// Load GPRs x8-x28, and save our SP/FP for later comparison
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ldr x2, =gpr_in
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add x2, x2, #64
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ldp x8, x9, [x2], #16
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ldp x10, x11, [x2], #16
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ldp x12, x13, [x2], #16
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ldp x14, x15, [x2], #16
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ldp x16, x17, [x2], #16
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ldp x18, x19, [x2], #16
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ldp x20, x21, [x2], #16
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ldp x22, x23, [x2], #16
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ldp x24, x25, [x2], #16
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ldp x26, x27, [x2], #16
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ldr x28, [x2], #8
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str x29, [x2], #8 // FP
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str x30, [x2], #8 // LR
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// Load FPRs if we're not doing SVE
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cbnz x0, 1f
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ldr x2, =fpr_in
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ldp q0, q1, [x2]
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ldp q2, q3, [x2, #16 * 2]
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ldp q4, q5, [x2, #16 * 4]
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ldp q6, q7, [x2, #16 * 6]
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ldp q8, q9, [x2, #16 * 8]
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ldp q10, q11, [x2, #16 * 10]
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ldp q12, q13, [x2, #16 * 12]
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ldp q14, q15, [x2, #16 * 14]
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ldp q16, q17, [x2, #16 * 16]
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ldp q18, q19, [x2, #16 * 18]
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ldp q20, q21, [x2, #16 * 20]
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ldp q22, q23, [x2, #16 * 22]
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ldp q24, q25, [x2, #16 * 24]
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ldp q26, q27, [x2, #16 * 26]
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ldp q28, q29, [x2, #16 * 28]
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ldp q30, q31, [x2, #16 * 30]
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1:
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// Load the SVE registers if we're doing SVE
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cbz x0, 1f
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ldr x2, =z_in
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ldr z0, [x2, #0, MUL VL]
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ldr z1, [x2, #1, MUL VL]
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ldr z2, [x2, #2, MUL VL]
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ldr z3, [x2, #3, MUL VL]
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ldr z4, [x2, #4, MUL VL]
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ldr z5, [x2, #5, MUL VL]
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ldr z6, [x2, #6, MUL VL]
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ldr z7, [x2, #7, MUL VL]
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ldr z8, [x2, #8, MUL VL]
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ldr z9, [x2, #9, MUL VL]
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ldr z10, [x2, #10, MUL VL]
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ldr z11, [x2, #11, MUL VL]
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ldr z12, [x2, #12, MUL VL]
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ldr z13, [x2, #13, MUL VL]
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ldr z14, [x2, #14, MUL VL]
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ldr z15, [x2, #15, MUL VL]
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ldr z16, [x2, #16, MUL VL]
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ldr z17, [x2, #17, MUL VL]
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ldr z18, [x2, #18, MUL VL]
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ldr z19, [x2, #19, MUL VL]
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ldr z20, [x2, #20, MUL VL]
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ldr z21, [x2, #21, MUL VL]
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ldr z22, [x2, #22, MUL VL]
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ldr z23, [x2, #23, MUL VL]
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ldr z24, [x2, #24, MUL VL]
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ldr z25, [x2, #25, MUL VL]
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ldr z26, [x2, #26, MUL VL]
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ldr z27, [x2, #27, MUL VL]
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ldr z28, [x2, #28, MUL VL]
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ldr z29, [x2, #29, MUL VL]
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ldr z30, [x2, #30, MUL VL]
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ldr z31, [x2, #31, MUL VL]
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ldr x2, =ffr_in
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ldr p0, [x2, #0]
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wrffr p0.b
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ldr x2, =p_in
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ldr p0, [x2, #0, MUL VL]
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ldr p1, [x2, #1, MUL VL]
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ldr p2, [x2, #2, MUL VL]
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ldr p3, [x2, #3, MUL VL]
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ldr p4, [x2, #4, MUL VL]
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ldr p5, [x2, #5, MUL VL]
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ldr p6, [x2, #6, MUL VL]
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ldr p7, [x2, #7, MUL VL]
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ldr p8, [x2, #8, MUL VL]
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ldr p9, [x2, #9, MUL VL]
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ldr p10, [x2, #10, MUL VL]
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ldr p11, [x2, #11, MUL VL]
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ldr p12, [x2, #12, MUL VL]
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ldr p13, [x2, #13, MUL VL]
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ldr p14, [x2, #14, MUL VL]
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ldr p15, [x2, #15, MUL VL]
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1:
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// Do the syscall
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svc #0
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// Save GPRs x8-x30
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ldr x2, =gpr_out
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add x2, x2, #64
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stp x8, x9, [x2], #16
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stp x10, x11, [x2], #16
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stp x12, x13, [x2], #16
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stp x14, x15, [x2], #16
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stp x16, x17, [x2], #16
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stp x18, x19, [x2], #16
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stp x20, x21, [x2], #16
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stp x22, x23, [x2], #16
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stp x24, x25, [x2], #16
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stp x26, x27, [x2], #16
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stp x28, x29, [x2], #16
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str x30, [x2]
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// Restore x0 and x1 for feature checks
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ldp x0, x1, [sp, #16]
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// Save FPSIMD state
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ldr x2, =fpr_out
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stp q0, q1, [x2]
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stp q2, q3, [x2, #16 * 2]
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stp q4, q5, [x2, #16 * 4]
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stp q6, q7, [x2, #16 * 6]
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stp q8, q9, [x2, #16 * 8]
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stp q10, q11, [x2, #16 * 10]
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stp q12, q13, [x2, #16 * 12]
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stp q14, q15, [x2, #16 * 14]
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stp q16, q17, [x2, #16 * 16]
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stp q18, q19, [x2, #16 * 18]
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stp q20, q21, [x2, #16 * 20]
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stp q22, q23, [x2, #16 * 22]
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stp q24, q25, [x2, #16 * 24]
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stp q26, q27, [x2, #16 * 26]
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stp q28, q29, [x2, #16 * 28]
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stp q30, q31, [x2, #16 * 30]
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// Save the SVE state if we have some
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cbz x0, 1f
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ldr x2, =z_out
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str z0, [x2, #0, MUL VL]
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str z1, [x2, #1, MUL VL]
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str z2, [x2, #2, MUL VL]
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str z3, [x2, #3, MUL VL]
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str z4, [x2, #4, MUL VL]
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str z5, [x2, #5, MUL VL]
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str z6, [x2, #6, MUL VL]
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str z7, [x2, #7, MUL VL]
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str z8, [x2, #8, MUL VL]
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str z9, [x2, #9, MUL VL]
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str z10, [x2, #10, MUL VL]
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str z11, [x2, #11, MUL VL]
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str z12, [x2, #12, MUL VL]
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str z13, [x2, #13, MUL VL]
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str z14, [x2, #14, MUL VL]
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str z15, [x2, #15, MUL VL]
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str z16, [x2, #16, MUL VL]
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str z17, [x2, #17, MUL VL]
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str z18, [x2, #18, MUL VL]
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str z19, [x2, #19, MUL VL]
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str z20, [x2, #20, MUL VL]
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str z21, [x2, #21, MUL VL]
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str z22, [x2, #22, MUL VL]
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str z23, [x2, #23, MUL VL]
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str z24, [x2, #24, MUL VL]
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str z25, [x2, #25, MUL VL]
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str z26, [x2, #26, MUL VL]
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str z27, [x2, #27, MUL VL]
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str z28, [x2, #28, MUL VL]
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str z29, [x2, #29, MUL VL]
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str z30, [x2, #30, MUL VL]
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str z31, [x2, #31, MUL VL]
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ldr x2, =p_out
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str p0, [x2, #0, MUL VL]
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str p1, [x2, #1, MUL VL]
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str p2, [x2, #2, MUL VL]
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str p3, [x2, #3, MUL VL]
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str p4, [x2, #4, MUL VL]
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str p5, [x2, #5, MUL VL]
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str p6, [x2, #6, MUL VL]
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str p7, [x2, #7, MUL VL]
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str p8, [x2, #8, MUL VL]
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str p9, [x2, #9, MUL VL]
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str p10, [x2, #10, MUL VL]
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str p11, [x2, #11, MUL VL]
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str p12, [x2, #12, MUL VL]
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str p13, [x2, #13, MUL VL]
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str p14, [x2, #14, MUL VL]
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str p15, [x2, #15, MUL VL]
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ldr x2, =ffr_out
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rdffr p0.b
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str p0, [x2, #0]
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1:
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// Restore callee saved registers x19-x30
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ldp x19, x20, [sp, #32]
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ldp x21, x22, [sp, #48]
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ldp x23, x24, [sp, #64]
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ldp x25, x26, [sp, #80]
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ldp x27, x28, [sp, #96]
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ldp x29, x30, [sp], #112
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ret
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