Zhan Liu 49a6ebb95d drm/amd/display: revert "Reset fifo after enable otg" ...

[Why]
This change causes regression, that prevents some systems
from lighting up internal displays.

[How]
Revert this patch until a new solution is ready.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

2022-02-02 18:35:00 -05:00

..

dcn20_dccg.c

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn20_dccg.h

drm/amd/display: Disable hdmistream and hdmichar clocks

2021-10-19 17:20:28 -04:00

dcn20_dpp_cm.c

drm/amd/display: Delete several unneeded bool conversions

2021-05-11 09:44:35 -04:00

dcn20_dpp.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn20_dpp.h

drm/amd/display: Add DSCL memory low power support

2020-12-01 16:03:40 -05:00

dcn20_dsc.c

drm/amd/display: fixed the DSC power off sequence during Driver PnP

2021-11-22 14:45:02 -05:00

dcn20_dsc.h

drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3

2020-08-17 14:09:27 -04:00

dcn20_dwb_scl.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn20_dwb.c

…

dcn20_dwb.h

…

dcn20_hubbub.c

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn20_hubbub.h

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn20_hubp.c

drm/amd/display: implement dc_mode_memclk

2021-12-14 16:08:41 -05:00

dcn20_hubp.h

drm/amd/display: implement dc_mode_memclk

2021-12-14 16:08:41 -05:00

dcn20_hwseq.c

drm/amd/display: access hpo dp link encoder only through link resource

2021-12-30 08:54:45 -05:00

dcn20_hwseq.h

drm/amd/display: implement dc_mode_memclk

2021-12-14 16:08:41 -05:00

dcn20_init.c

drm/amd: append missing includes

2021-12-13 16:32:34 -05:00

dcn20_init.h

drm/amd/display: cleanup of function pointer tables

2019-11-19 10:12:53 -05:00

dcn20_link_encoder.c

drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

2021-04-09 16:38:31 -04:00

dcn20_link_encoder.h

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04 17:11:37 -05:00

dcn20_mmhubbub.c

…

dcn20_mmhubbub.h

drm/amd/display: Update register defines

2020-02-11 11:50:18 -05:00

dcn20_mpc.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn20_mpc.h

drm/amd/display: Use cursor locking to prevent flip delays

2020-04-28 16:19:56 -04:00

dcn20_opp.c

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

dcn20_opp.h

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

dcn20_optc.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn20_optc.h

drm/amd/display: fixed the DSC power off sequence during Driver PnP

2021-11-22 14:45:02 -05:00

dcn20_resource.c

drm/amd/display: Changed pipe split policy to allow for multi-display pipe split

2021-12-30 08:54:44 -05:00

dcn20_resource.h

drm/amd/display: Move specific DCN2x code that uses FPU to DML

2021-08-05 21:17:59 -04:00

dcn20_stream_encoder.c

drm/amd/display: revert "Reset fifo after enable otg"

2022-02-02 18:35:00 -05:00

dcn20_stream_encoder.h

drm/amd/display: Add DPCD writes at key points

2021-09-14 15:57:09 -04:00

dcn20_vmid.c

drm/amd/display: Poll for GPUVM context ready (v2)

2019-07-18 14:18:09 -05:00

dcn20_vmid.h

drm/amd/display: Update register defines

2020-02-11 11:50:18 -05:00

Makefile

drm/amdgpu/display: drop DCN support for aarch64

2021-01-05 11:35:53 -05:00