aa5b537b0e
Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
23 lines
1009 B
Makefile
23 lines
1009 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o
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obj-$(CONFIG_ARM_CCN) += arm-ccn.o
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obj-$(CONFIG_ARM_CMN) += arm-cmn.o
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obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o
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obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
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obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
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obj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o
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obj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o
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obj-$(CONFIG_HISI_PMU) += hisilicon/
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obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
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obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
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obj-$(CONFIG_RISCV_PMU) += riscv_pmu.o
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obj-$(CONFIG_RISCV_PMU_LEGACY) += riscv_pmu_legacy.o
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obj-$(CONFIG_RISCV_PMU_SBI) += riscv_pmu_sbi.o
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obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
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obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o
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obj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o
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