b738c106f7
Add some other common headers for basic LoongArch support. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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#include <linux/types.h>
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#include <asm/asm.h>
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#define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
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#define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
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#define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
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#define ADDR_IMMSHIFT_LU52ID 52
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#define ADDR_IMMSHIFT_LU32ID 32
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#define ADDR_IMMSHIFT_ADDU16ID 16
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#define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
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enum reg1i20_op {
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lu12iw_op = 0x0a,
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lu32id_op = 0x0b,
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};
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enum reg2i12_op {
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lu52id_op = 0x0c,
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};
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enum reg2i16_op {
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jirl_op = 0x13,
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};
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struct reg0i26_format {
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unsigned int immediate_h : 10;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg1i20_format {
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unsigned int rd : 5;
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unsigned int immediate : 20;
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unsigned int opcode : 7;
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};
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struct reg1i21_format {
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unsigned int immediate_h : 5;
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unsigned int rj : 5;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg2i12_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 12;
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unsigned int opcode : 10;
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};
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struct reg2i16_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 16;
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unsigned int opcode : 6;
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};
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union loongarch_instruction {
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unsigned int word;
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struct reg0i26_format reg0i26_format;
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struct reg1i20_format reg1i20_format;
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struct reg1i21_format reg1i21_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i16_format reg2i16_format;
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};
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#define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
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enum loongarch_gpr {
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LOONGARCH_GPR_ZERO = 0,
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LOONGARCH_GPR_RA = 1,
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LOONGARCH_GPR_TP = 2,
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LOONGARCH_GPR_SP = 3,
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LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
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LOONGARCH_GPR_A1, /* Reused as V1 for return value */
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LOONGARCH_GPR_A2,
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LOONGARCH_GPR_A3,
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LOONGARCH_GPR_A4,
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LOONGARCH_GPR_A5,
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LOONGARCH_GPR_A6,
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LOONGARCH_GPR_A7,
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LOONGARCH_GPR_T0 = 12,
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LOONGARCH_GPR_T1,
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LOONGARCH_GPR_T2,
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LOONGARCH_GPR_T3,
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LOONGARCH_GPR_T4,
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LOONGARCH_GPR_T5,
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LOONGARCH_GPR_T6,
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LOONGARCH_GPR_T7,
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LOONGARCH_GPR_T8,
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LOONGARCH_GPR_FP = 22,
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LOONGARCH_GPR_S0 = 23,
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LOONGARCH_GPR_S1,
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LOONGARCH_GPR_S2,
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LOONGARCH_GPR_S3,
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LOONGARCH_GPR_S4,
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LOONGARCH_GPR_S5,
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LOONGARCH_GPR_S6,
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LOONGARCH_GPR_S7,
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LOONGARCH_GPR_S8,
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LOONGARCH_GPR_MAX
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};
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u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
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u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
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u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);
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#endif /* _ASM_INST_H */
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