linux/drivers/clk/rockchip
Douglas Anderson 00c0cd9e59 clk: rockchip: Fix video codec clocks on rk3288
It appears that there is a typo in the rk3288 TRM.  For
GRF_SOC_CON0[7] it says that 0 means "vepu" and 1 means "vdpu".  It's
the other way around.

How do I know?  Here's my evidence:

1. Prior to commit 4d3e84f996 ("clk: rockchip: describe aclk_vcodec
   using the new muxgrf type on rk3288") we always pretended that we
   were using "aclk_vdpu" and the comment in the code said that this
   matched the default setting in the system.  In fact the default
   setting is 0 according to the TRM and according to reading memory
   at bootup.  In addition rk3288-based Chromebooks ran like this and
   the video codecs worked.
2. With the existing clock code if you boot up and try to enable the
   new VIDEO_ROCKCHIP_VPU as a module (and without "clk_ignore_unused"
   on the command line), you get errors like "failed to get ack on
   domain 'pd_video', val=0x80208".  After flipping vepu/vdpu things
   init OK.
3. If I export and add both the vepu and vdpu to the list of clocks
   for RK3288_PD_VIDEO I can get past the power domain errors, but now
   I freeze when the vpu_mmu gets initted.
4. If I just mark the "vdpu" as IGNORE_UNUSED then everything boots up
   and probes OK showing that somehow the "vdpu" was important to keep
   enabled.  This is because we were actually using it as a parent.
5. After this change I can hack "aclk_vcodec_pre" to parent from
   "aclk_vepu" using assigned-clocks and the video codec still probes
   OK.
6. Rockchip has said so on the mailing list [1].

...so let's fix it.

Let's also add CLK_SET_RATE_PARENT to "aclk_vcodec_pre" as suggested
by Jonas Karlman.  Prior to the same commit you could do
clk_set_rate() on "aclk_vcodec" and it would change "aclk_vdpu".
That's because "aclk_vcodec" was a simple gate clock (always gets
CLK_SET_RATE_PARENT) and its direct parent was "aclk_vdpu".  After
that commit "aclk_vcodec_pre" gets in the way so we need to add
CLK_SET_RATE_PARENT to it too.

[1] https://lkml.kernel.org/r/1d17b015-9e17-34b9-baf8-c285dc1957aa@rock-chips.com

Fixes: 4d3e84f996 ("clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Suggested-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 11:27:46 +02:00
..
clk-cpu.c clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk() 2017-09-28 15:22:50 +02:00
clk-ddr.c clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call 2018-10-17 15:12:51 +02:00
clk-half-divider.c clk: rockchip: add support for half divider 2018-07-06 19:17:57 +02:00
clk-inverter.c clk: rockchip: don't return NULL when registering inverter fails 2016-02-15 23:35:20 +01:00
clk-mmc-phase.c clk: rockchip: Fix error return in phase clock registration 2018-03-23 09:08:43 +01:00
clk-muxgrf.c clk: rockchip: add a clock-type for muxes based in the grf 2017-01-02 14:24:57 +01:00
clk-pll.c clk: rockchip: add pll_wait_lock for pll_enable 2017-03-22 18:33:22 +01:00
clk-px30.c clk: rockchip: add clock controller for px30 2018-07-06 19:17:57 +02:00
clk-rk3036.c clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 2017-06-02 15:42:38 +02:00
clk-rk3128.c clk: rockchip: add sclk_timer5 as critical clock on rk3128 2017-09-17 01:55:36 +02:00
clk-rk3188.c clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks 2019-01-07 09:17:15 +01:00
clk-rk3228.c clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228 2018-03-23 08:49:35 +01:00
clk-rk3288.c clk: rockchip: Fix video codec clocks on rk3288 2019-04-12 11:27:46 +02:00
clk-rk3328.c clk: rockchip: fix wrong clock definitions for rk3328 2019-03-18 08:45:55 +01:00
clk-rk3368.c clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs 2017-10-14 21:31:58 +02:00
clk-rk3399.c clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 2018-08-06 23:46:52 +02:00
clk-rv1108.c clk: rockchip: fix the rv1108 clk_mac sel register description 2017-08-22 02:55:03 +02:00
clk.c clk: rockchip: add support for half divider 2018-07-06 19:17:57 +02:00
clk.h clk: rockchip: add clock controller for px30 2018-07-06 19:17:57 +02:00
Makefile clk: rockchip: add clock controller for px30 2018-07-06 19:17:57 +02:00
softrst.c clk: rockchip: Make reset_control_ops const 2016-03-29 16:29:46 -07:00